Electric circuit for decoding a two-phase asynchronous data signal and corresponding decoding method, device for controlling equipment

• US 20050117671A1
• Filed: 11/17/2004
• Published: 06/02/2005
• Est. Priority Date: 11/21/2003
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Nantes SAS (Microchip Technology Incorporated)
• Inventors: Letendu, Raphael, Aubree, Rene
• Granted Patent: US 7,151,811 B2
• Time in Patent Office: Days
• US Class Current: 375/333
• CPC Class Codes: H03M 5/12 Biphase level code, e.g. split phase code, Manchester code; Biphase space or mark code, e.g. double frequency code

Abstract

This invention relates to an electronic circuit for decoding an asynchronous two-phase data signal. According to the invention, such an electronic circuit comprises means for generating a decoding clock using a counter powered by an internal clock, and repeating cycles including incrementation of the said counter until detection of a transition in the said data signal, followed by decrementing the said counter down to zero.

Claims

1. Electronic circuit for decoding an asynchronous two-phase data signal,

wherein it comprises means for generating a decoding clock using a counter feeded by an internal clock, and repeating cycles including incrementation of the said counter until detection of a transition in the said data signal, followed by decrementing the said counter down to zero.

2. Electronic circuit according to claim 1, wherein the said decoding clock is generated by taking into account each peak of a signal representative of the contents of the said counter.

3. Electronic circuit according to claim 2, wherein each of the said peaks is used to mark a transition that transports the value of a bit of the said data signal.

4. Electronic circuit according to claim 3, wherein the direction of each of the said transitions is analysed to decode the value of a bit of the said data signal.

5. Electronic circuit according to claim 1, wherein it comprises at least one register for memorising the contents of the said counter when the said detection of a transition occurs in the said data signal.

6. Electronic circuit according to claim 1, wherein it comprises initialisation means which, during the first falling front, activate incrementation of the said counter, the counter being forced to zero before starting.

7. Electronic circuit according to claim 1, wherein it comprises windowing means limiting the said detection of a transition on predetermined intervals.

8. Electronic circuit according to claim 7, wherein each of the said predetermined intervals covers approximately 50% of a binary time and is centred on the said transitions.

9. Electronic circuit according to claim 7, wherein the said predetermined interval is controlled by a first comparator feeded by the output from the memory register divided by two, and by the said counter.

10. Electronic circuit according to claim 1, wherein it comprises means for detecting interruption of the said data signal.

11. Electronic circuit according to claim 10, wherein the said interruption detection means include a second comparator feeded by the output from the memory register multiplied by two, and by the said counter.

12. Electronic circuit according to claim 1, wherein it comprises means for rejecting parasites on the said data signal.

13. Electronic circuit according to claim 12, wherein the said rejection means include a digital filter feeded by the said data signal and controlled by the said internal clock.

14. Electronic circuit according to claim 12, wherein the said rejection means use at least three successive samples to decide on whether or not one of the said transitions exists.

15. Electronic circuit according to claim 1, wherein the said internal clock has a frequency at least 16 times greater than the said data signal rate.

16. Electronic circuit according to claim 1, wherein the said data signal is encoded using Manchester encoding.

17. Electronic circuit according to claim 1, wherein the said data signal is organised into successive frames each beginning with a start bit.

18. Electronic circuit according to claim 1, wherein it can receive and decode a sequence comprising an undefined number of data.

19. Method for decoding a two-phase asynchronous data frame,

wherein it comprises steps for generating a decoding clock using a counter feeded by an internal clock, and repeating cycles including incrementation of the said counter until detection of a transition in the said data signal, followed by decrementing the counter down to zero.

20. Control device of at least one equipment,

wherein it comprises an electronic circuit for decoding a two-phase asynchronous data signal, comprising means for generating a decoding clock using a counter feeded by an internal clock, and repeating cycles including incrementation of the said counter until detection of a transition in the said data signal, followed by decrementing the said counter down to zero.

21. Control device according to claim 20, wherein the said equipment is a lighting equipment.