Electric circuit for decoding a two-phase asynchronous data signal and corresponding decoding method, device for controlling equipment
First Claim
1. Electronic circuit for decoding an asynchronous two-phase data signal, wherein it comprises means for generating a decoding clock using a counter feeded by an internal clock, and repeating cycles including incrementation of the said counter until detection of a transition in the said data signal, followed by decrementing the said counter down to zero.
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Abstract
This invention relates to an electronic circuit for decoding an asynchronous two-phase data signal. According to the invention, such an electronic circuit comprises means for generating a decoding clock using a counter powered by an internal clock, and repeating cycles including incrementation of the said counter until detection of a transition in the said data signal, followed by decrementing the said counter down to zero.
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Citations
21 Claims
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1. Electronic circuit for decoding an asynchronous two-phase data signal,
wherein it comprises means for generating a decoding clock using a counter feeded by an internal clock, and repeating cycles including incrementation of the said counter until detection of a transition in the said data signal, followed by decrementing the said counter down to zero.
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19. Method for decoding a two-phase asynchronous data frame,
wherein it comprises steps for generating a decoding clock using a counter feeded by an internal clock, and repeating cycles including incrementation of the said counter until detection of a transition in the said data signal, followed by decrementing the counter down to zero.
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20. Control device of at least one equipment,
wherein it comprises an electronic circuit for decoding a two-phase asynchronous data signal, comprising means for generating a decoding clock using a counter feeded by an internal clock, and repeating cycles including incrementation of the said counter until detection of a transition in the said data signal, followed by decrementing the said counter down to zero.
Specification