Methods of fabricating semiconductor-on-insulator (SOI) substrates and semiconductor devices using sacrificial layers and void spaces, and SOI substrates and devices fabricated thereby

• US 20050118783A1
• Filed: 10/25/2004
• Published: 06/02/2005
• Est. Priority Date: 11/27/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Sung-Young, Park, Dong-Gun, Choe, Jeong-Dong, Oh, Chang-Woo
• Granted Patent: US 7,265,031 B2
• Time in Patent Office: Days
• US Class Current: 438/421
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence

Abstract

An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining.

Claims

1. A method for fabricating an SOI substrate, comprising:

forming a stack pattern including a sacrificial layer and an active semiconductor layer in sequence on a substrate, the sacrificial layer being formed of a material having etch selectivity with respect to the substrate and the active semiconductor layer;

forming a supporting pattern contacting at least two sides of the stack pattern on the substrate that exposes at least one side of the sacrificial layer and the active semiconductor layer on at least one side of the stack pattern; and

selectively etching the sacrificial layer through at least one side thereof that is exposed, to form a void space between the substrate and the active semiconductor layer.

2. The method as claimed in claim 1, wherein forming the supporting pattern comprises:

forming a supporting layer contacting all sides of the stack pattern on the exposed substrate; and

patterning the supporting layer to expose at least one side of the sacrificial layer and the active semiconductor layer.

3. The method as claimed in claim 1:

wherein forming a stack pattern is preceded by forming a supporting layer that surrounds a formation region of the stack pattern on the semiconductor substrate;

wherein forming the stack pattern comprises forming the sacrificial layer and the active semiconductor layer on the exposed semiconductor substrate such that sides of the sacrificial layer and the active semiconductor layer come into contact with the supporting layer; and

wherein forming the supporting pattern comprises patterning the supporting layer to expose at least one side of the sacrificial layer and the active semiconductor layer.

4. The method as claimed in claim 2, wherein forming the stack pattern comprises:

sequentially epitaxially growing the sacrificial layer and the active semiconductor layer on the substrate; and

patterning the sacrificial layer and the active semiconductor layer.

5. The method as claimed in claim 1, wherein selectively etching is followed by:

forming a supporting layer that covers at least one exposed side of the active semiconductor layer and the void space.

6. The method as claimed in claim 1, wherein forming a supporting pattern comprises etching portions of the active layer and the sacrificial layer that are not in contact with the supporting pattern.

7. The method as claimed in claim 1, wherein selectively etching is followed by:

forming an insulating layer between the substrate and the active semiconductor layer to at least partially fill the void space.

8. The method as claimed in claim 1, wherein selectively etching is followed by:

forming a thermal oxidation layer on a surface of the substrate facing the active semiconductor layer and on a surface of the active semiconductor layer facing the substrate.

9. The method as claimed in claim 1, further comprising:

reducing a thickness of the active layer.

10. The method as claimed in claim 1, wherein the substrate is a Si semiconductor substrate, and the sacrificial layer and the active semiconductor layer comprise a SiGe layer and a Si layer, respectively.

11. A method for fabricating an SOI substrate, comprising:

forming a supporting pattern on a substrate that exposes a portion of the substrate;

forming a sacrificial layer and an active semiconductor layer in sequence on the exposed portion of the substrate, such that at least two sides of the sacrificial layer and the active layer come into contact with the supporting pattern and at least one side of the sacrificial layer and the active semiconductor layer are exposed, the sacrificial layer being formed of a material having etch selectivity with respect to the substrate and the active semiconductor layer; and

forming a void space between the substrate and the active semiconductor layer by selectively removing the sacrificial layer through at least one side thereof that is exposed.

12. The method as claimed in claim 11, wherein forming a void space is followed by:

forming a supporting layer that covers at least one exposed side of the active semiconductor layer and the void space.

13. The method as claimed in claim 11, wherein forming a void space is followed by:

forming an insulating layer between the substrate and the active semiconductor layer to at least partially fill the void space.

14. The method as claimed in claim 11, wherein forming a void space is followed by:

forming a thermal oxidation layer on a surface of the substrate facing the active semiconductor layer and on a surface of the active semiconductor layer facing the substrate.

15. The method as claimed in claim 11, further comprising:

reducing a thickness of the active layer.

16. The method as claimed in claim 11, wherein the substrate is a Si semiconductor substrate, and the sacrificial layer and the active semiconductor layer comprise a SiGe layer and a Si layer, respectively.

17. A method for fabricating a semiconductor device, comprising:

epitaxially growing a sacrificial layer and an active semiconductor layer on a substrate in sequence, with the sacrificial layer being formed of a material having etch selectivity with respect to the substrate and the active semiconductor layer;

patterning the active layer and the sacrificial layer to expose portions of the substrate in a device isolation region;

forming a first device isolation layer contacting at least two sides of the patterned active semiconductor layer and sacrificial layer on the exposed portions of the substrate;

exposing at least one side of the active semiconductor layer and the sacrificial layer;

forming a void space between the substrate and the active semiconductor layer by selectively removing the sacrificial layer through at least one side thereof that is exposed, with the first device isolation layer being used as a supporting layer of the active layer;

forming a second device isolation layer to cover the exposed side of the active semiconductor layer and the void space; and

forming a gate electrode on the active layer.

18. The method as claimed in claim 17, wherein the following is performed between forming a second device isolation layer and forming a gate electrode:

removing portions of the first and second device isolation layers to expose a side of the active semiconductor layer, and

wherein forming the gate electrode comprises forming a gate electrode that extends on an upper surface and the side of the active semiconductor layer.

19. The method as claimed in claim 18, further comprising oxidizing the side of the active layer after exposing the side of the active semiconductor layer.

20. The method as claimed in claim 17, wherein forming the gate electrode comprises:

selectively etching the active layer to form a trench; and

forming the gate electrode at least partially within the trench.

21. The method as claimed in claim 17, wherein forming the first device isolation layer comprises:

forming an insulating layer contacting all sides of the active layer and the sacrificial layer on the exposed substrate; and

patterning the insulating layer to expose at least two sides of the sacrificial layer and the active semiconductor layer.

22. The method as claimed in claim 17, wherein exposing at least one side of the active semiconductor layer and the sacrificial layer comprises removing at least a portion of the active semiconductor layer and the sacrificial layer that are not in contact with the first device isolation layer.

23. The method as claimed in claim 17, wherein forming a void space is followed by:

forming an insulating layer between the substrate and the active semiconductor layer to at least partially fill the void space.

24. The method as claimed in claim 17, wherein forming a void space is followed by:

forming a thermal oxidation layer on a surface of the substrate facing the active semiconductor layer and on a surface of the active semiconductor layer facing the substrate.

25. The method as claimed in claim 17, further comprising:

reducing a thickness of the active layer.

26. The method as claimed in claim 17, wherein the substrate is a Si semiconductor substrate, and the sacrificial layer and the active semiconductor layer comprise a SiGe layer and a Si layer, respectively.

27. A method for fabricating a semiconductor device, comprising:

forming an insulating layer on a device isolation region on a substrate that exposes a portion of the substrate;

forming a sacrificial layer and an active semiconductor layer in sequence on the exposed portion of the substrate, such that at least two sides of the sacrificial layer and active layer come into contact with the insulating layer, the sacrificial layer being formed of a material having etch selectivity with respect to the substrate and the active semiconductor layer;

patterning the insulating layer to form a first device isolation layer that covers at least two sides of the sacrificial layer and the active semiconductor layer and that exposes at least one side of the sacrificial layer and the active semiconductor layer;

forming a void space between the substrate and the active semiconductor layer by selectively removing the sacrificial layer through the at least one side thereof that is exposed, with the first device isolation layer being used as a supporting layer of the active layer;

forming a second device isolation layer to cover the at least one exposed side of the active semiconductor layer and the void space; and

forming a gate electrode on the active layer.

28. The method as claimed in claim 27, wherein the following is performed between forming a second device isolation layer and forming a gate electrode:

removing portions of the first and second device isolation layers to expose a side of the active layer, and

wherein forming the gate electrode comprises forming a gate electrode that extends on an upper surface and the side of the active semiconductor layer.

29. The method as claimed in claim 28, further comprising oxidizing the side of the active layer after exposing the side of the active semiconductor layer.

30. The method as claimed in claim 27, wherein forming a void space is followed by:

forming an insulating layer between the substrate and the active semiconductor layer to at least partially fill the void space.

31. The method as claimed in claim 27, further comprising:

reducing a thickness of the active layer.

32. The method as claimed in claim 27, wherein the substrate is a Si semiconductor substrate, and the sacrificial layer and the active semiconductor layer comprise a SiGe layer and a Si layer, respectively.

33. A method for fabricating a semiconductor device, comprising:

forming a first device isolation layer that covers portions of a device isolation region on a substrate and that exposes a portion of the substrate;

forming a sacrificial layer and an active semiconductor layer in sequence on the exposed portion of the substrate, such that at least two sides of the sacrificial layer and the active semiconductor layer come into contact with the first device isolation layer, the sacrificial layer being formed of a material having etch selectivity with respect to the semiconductor substrate and the active layer;

selectively etching the active layer and the sacrificial layer that are not in contact with the first device isolation layer to expose at least one other side of the sacrificial layer and the active layer;

forming a void space between the semiconductor substrate and the active layer by selectively removing the sacrificial layer through the at least one other side of the sacrificial layer, with the first device isolation layer being used as a supporting layer of the active layer;

forming a second device isolation layer that covers the exposed sides of the active semiconductor layer and the void space; and

forming a gate electrode on the active layer.

34. The method as claimed in claim 33, wherein the following is performed between forming a second device isolation layer and forming a gate electrode:

removing portions of the first and second device isolation layers to expose a side of the active layer, and

wherein forming the gate electrode comprises forming a gate electrode that extends on an upper surface and the side of the active semiconductor layer.

35. The method as claimed in claim 34, further comprising oxidizing the side of the active layer after exposing the side of the active semiconductor layer.

36. The method as claimed in claim 34, wherein forming a void space is followed by:

forming an insulating layer between the substrate and the active semiconductor layer to at least partially fill the void space.

37. The method as claimed in claim 33, further comprising:

reducing a thickness of the active layer.

38. The method as claimed in claim 33, wherein the substrate is a Si semiconductor substrate, and the sacrificial layer and the active semiconductor layer comprise a SiGe layer and a Si layer, respectively.

39. A semiconductor device, comprising:

a semiconductor substrate;

a device isolation layer on the semiconductor substrate; and

an active semiconductor layer spaced apart from the semiconductor substrate with a void space interposed therebetween, supported by the device isolation layer, and having a lattice constant close to that of the semiconductor substrate.

40. The semiconductor device as claimed in claim 39, further comprising a gate electrode within the active layer or on the active layer remote from the semiconductor substrate.

41. The semiconductor device as claimed in claim 40, wherein the gate electrode also extends on a side of the active semiconductor layer.

42. The semiconductor device as claimed in claim 41, wherein the gate electrode covers a surface of the active semiconductor layer remote from the semiconductor substrate.

43. The semiconductor device as claimed in claim 39, wherein selectively etching is followed by:

forming an insulating layer on a surface of the substrate facing the active semiconductor layer and on a surface of the active semiconductor layer facing the substrate.

44. The semiconductor device as claimed in claim 39, wherein the semiconductor substrate is a Si substrate, and the active semiconductor layer is a Si epitaxial layer.

45. A method for fabricating an SOI substrate comprising:

providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer; and

etching at least some of the sacrificial layer through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer.

46. A method according to claim 45 wherein etching is followed by at least partially filling the void space with an insulating layer.

47. A method according to claim 45 wherein the substrate is a semiconductor substrate, wherein the sacrificial layer is an epitaxial sacrificial layer and wherein the active semiconductor layer is an epitaxial active semiconductor layer.