Methods of operation of a memory device and system

• US 20050120161A1
• Filed: 11/19/2004
• Published: 06/02/2005
• Est. Priority Date: 03/10/1998
• Status: Active Grant

• Current Assignee: Bradley A. May, Craig E. Hampel, Ely K. Tsern, Frederick A. Ware, Paul G. Davis, Richard M. Barth, Todd W. Bystrom
• Original Assignee: Bradley A. May, Craig E. Hampel, Ely K. Tsern, Frederick A. Ware, Paul G. Davis, Richard M. Barth, Todd W. Bystrom
• Inventors: Barth, Richard M., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A., Davis, Paul G., Bystrom, Todd W., May, Bradley A.
• Granted Patent: US 8,127,152 B2
• Time in Patent Office: Days
• US Class Current: 711/100
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.

Claims

1-24. -24. (canceled)

25. A method of operation of a memory device having an array of memory cells, the method comprising:

during an initialization sequence, conducting initialization operations at a first frequency of operation; and

performing memory access operations at a second frequency of operation, wherein the second frequency is higher than the first frequency, wherein the memory access operations include a read operation and a write operation.

26. The method of claim 25, wherein the second frequency is higher than the first frequency by several hundred megahertz.

27. The method of claim 26, wherein the second frequency is approximately equal to four hundred megahertz and the first frequency is approximately equal to one megahertz.

28. The method of claim 26, wherein the second frequency is approximately equal to fifty megahertz and the first frequency is approximately equal to one megahertz

29. The method of claim 25, further including transitioning operation of the memory device from the first frequency of operation to the second frequency of operation.

30. The method of claim 25, further including, during the initialization sequence, storing a value representative of a period of time to elapse between exiting from a power down mode and a time at which the memory device is capable of receiving a command, wherein the command specifies one of the memory access operations.

31. The method of claim 30, further including receiving the command, wherein the command specifies the write operation, wherein the memory device inputs data to be written to the array of memory cells during the write operation.

32. The method of claim 30, further including receiving the command, wherein the command specifies the read operation, wherein the memory device outputs read data accessed from the array of memory cells during the read operation.

33. The method of claim 32, further including:

synchronizing the output of the read data with a clock signal using a delay lock loop circuit; and

outputting the read data using the clock signal, wherein the clock signal oscillates at the second frequency of operation.

34. The method of claim 25, further including:

receiving a first clock signal, wherein the first clock frequency oscillates at the first frequency of operation; and

receiving a second clock signal, wherein the second clock frequency oscillates at the second frequency of operation.

35. The method of claim 25, further including:

during the initialization sequence;

receiving power;

after receiving power, starting a clock signal; and

receiving an initialization command, after an amount of time has elapsed from starting the clock signal.

36. The method of claim 25, further including, during the initialization sequence, programming a plurality of registers on the memory device, the plurality of registers to store a plurality of values that configure operation of the memory device in accordance with a plurality of timing parameters.

37. The method of claim 36, wherein the plurality of timing parameters includes:

a time to access a row of the memory device;

a time between a row access of the memory device and a column access of the memory device;

a time between a row access of the memory device and a precharge operation of the memory device;

a time between a row sense applied to a first bank of the memory device and a row sense applied to a second bank of the memory device; and

a time between a precharge operation applied to a first bank of the memory device and a precharge operation applied to a second bank of the memory device.

38. The method of claim 36, wherein each value is selected based on information stored in a serial presence detect device, wherein the serial presence detect device is included, with the memory device, on a memory module.

39. The method of claim 36, wherein each value of the plurality of values represents a number of clock cycles of a clock signal for each timing parameter of the plurality of timing parameters.

40. The method of claim 39, wherein each value is selected by dividing a time period of each timing parameter by the period of the clock signal to select the value in terms of the number of clock cycles of the clock signal.

41. The memory device of claim 25, wherein the memory access operations are performed during the initialization procedure.

42. The method of claim 25, further comprising storing a value that represents a number of clock cycles between receiving a read request and outputting data, wherein the value is selected to levelize a read domain of the memory device with a read domain of other memory devices in a system, wherein storing the value is performed during the initialization sequence.

43. A method of controlling a memory device, the method comprising:

providing to the memory device during an initialization sequence, commands to conduct initialization operations at a first frequency of operation; and

providing a command to the memory device that specifies a memory access operation, wherein the memory access operation is conducted at a second frequency of operation, wherein the second frequency is higher than the first frequency.

44. The method of claim 43, further including, during the initialization sequence, providing a value to the memory device, wherein the value is representative of a period of time to elapse between exiting from a power down mode and a time at which the memory device is capable of receiving the command that specifies the memory access operation.

45. The method of claim 44, wherein the command that specifies the memory access operation specifies a read operation, wherein the memory device outputs data accessed from the array of memory cells during the read operation.

46. The method of claim 43, further including, during the initialization sequence, providing, to the memory device, a value that is representative of a number of clock cycles of a clock signal to separate a row command and a column command.

47. The method of claim 43, wherein providing the command that specifies the memory access operation is provided during the initialization sequence.

48. The method of claim 43, further including, during the initialization sequence, determining a value that is representative of a number of clock cycles of a clock signal to separate receipt of a read command by the memory device and data output in response to the read command by the memory device, wherein determining the value is conducted to levelize a read response time of the memory device with a read response time of other memory devices in a system.

49. The method of claim 43, further including, during the initialization sequence, providing an initialization command to the memory device after an amount of time has elapsed between a clock signal being started and a time at which the memory device is ready to receive the initialization command.

50. The method of claim 43, further including, during the initialization sequence, programming a plurality of registers on the memory device, the plurality of registers to store a plurality of values that configure operation of the memory device in accordance with a plurality of timing parameters.

51. The method of claim 43, further including generating a plurality of values to configure operation of the memory device in accordance with a plurality of timing parameters, wherein the plurality of timing parameters includes:

a time to access a row of the memory device;

a time between a row access of the memory device and a column access of the memory device;

a time between a row access of the memory device and a precharge operation of the memory device;

a time between a row sense applied to a first bank of the memory device and a row sense applied to a second bank of the memory device; and

a time between a precharge operation applied to a first bank of the memory device and a precharge operation applied to a second bank of the memory device.

52. The method of claim 51, wherein each value of the plurality of values represents a number of clock cycles of the clock signal for each timing parameter of the plurality of timing parameters.

53. The method of claim 51, further including, during the initialization sequence, selecting each value of the plurality of values based on information stored in a serial presence detect device, wherein the serial presence detect device is included, with the memory device, on a memory module.

54. The method of claim 53, wherein selecting each value of the plurality of values includes dividing a time period of each timing parameter by the period of a clock signal to select each value in terms of a number of clock cycles of the clock signal.

55. The method of claim 54, wherein selecting each value further includes rounding each value to a next whole number if a fractional number of clock cycles results when dividing the time period by the period of the clock signal.

56. A method of operation in a system that includes a memory module having a serial presence detect device and a memory device, the method comprising:

reading from the serial presence detect device, information that represents a first clock frequency used to conduct memory access operations, and a second clock frequency used to conduct initialization operations;

providing a command, at a first clock frequency, to the memory device during an initialization operation; and

providing commands to the memory device that specify memory access operations, wherein the memory access operations are conducted at the second clock frequency.

57. The method of claim 56, wherein the second clock frequency is higher than the first clock frequency by several hundred megahertz.

58. The method of claim 56, wherein the second clock frequency is approximately equal to four hundred megahertz and the first clock frequency is approximately equal to one megahertz.

59. The method of claim 56, wherein the second clock frequency is approximately equal to fifty megahertz and the first clock frequency is approximately equal to one megahertz

60. The method of claim 56, further including, during the initialization operation:

calculating a value representative of a period of time to elapse between the memory device exiting from a power down mode and a time at which the memory device is capable of receiving a command; and

storing the value in the memory device.

61. The method of claim 56, further including, during the initialization operation:

determining a value that represents a number of clock cycles separating a command that specifies activating a row in the memory device and a command that specifies a read operation to the memory device; and

storing the value in a memory controller that controls operation of the memory device.

62. The method of claim 56, further including:

providing power to the memory device;

after providing the power, starting a clock signal; and

providing an initialization command to the memory device, after an amount of time has elapsed between starting the clock signal and a time at which the memory device is ready to receive the initialization command.

63. The method of claim 56, further including:

reading from the serial presence detect device, a plurality of timing parameters that pertain to the memory device;

generating a value for each timing parameter of the plurality of timing parameters, wherein the value represents a corresponding timing parameter of the plurality of timing parameters in terms of clock cycles of a clock signal at the second clock frequency; and

storing the value in a register on the memory device to configure the memory device for operation.

64. The method of claim 63, wherein generating the value includes dividing a time of a timing parameter of the plurality of timing parameters by the period of the second clock frequency.

65. The method of claim 64, wherein generating the value further includes rounding the value to a next whole number if a fractional number of clock cycles results when dividing the time period by the period of the second clock frequency.

66. The method of claim 65, further including transitioning the memory device from operation at the first clock frequency to operation at the second clock frequency.

67. The method of claim 63, wherein the plurality of timing parameters includes:

a time to access a row of the memory device;

a time between a row access of the memory device and a column access of the memory device;

a time between a row access of the memory device and a precharge operation of the memory device;

a time between a row sense applied to a first bank of the memory device and a row sense applied to a second bank of the memory device; and

a time between a precharge operation applied to a first bank of the memory device and a precharge operation applied to a second bank of the memory device.

68. A method of initializing a memory device included on a memory module, the method comprising:

providing a command, at a first clock frequency, to the memory device during an initialization operation;

reading from a storage area located on the memory module, information that represents a timing parameter that pertains to the memory device;

converting the information that represents the timing parameter to a value expressed in terms of a number of clock cycles at a second clock frequency; and

providing the value to the memory device, wherein the memory device stores the value in a register to configure the memory device for memory access operations at the second clock frequency.

69. The method of claim 68, wherein converting the information includes dividing a time period pertaining to the timing parameter by a period of the second clock frequency.

70. The method of claim 69, wherein converting the information further includes rounding the value to a next whole number if a fractional number of clock cycles results when dividing the time period by the period of the second clock frequency.

71. The method of claim 70, further including reading information that represents the second clock frequency from the storage area.

72. The method of claim 68, wherein the timing parameter is a time to sense a row of the memory device.

73. The method of claim 68, wherein the timing parameter is a time between a row access operation of the memory device and column access operation of the memory device.

74. The method of claim 68, wherein the timing parameter is a time between a row access operation of the memory device and a precharge operation of the memory device.

75. The method of claim 68, wherein the timing parameter includes a time between a row sense operation applied to a first bank of the memory device and a row sense operation applied to a second bank of the memory device.

76. The method of claim 68, wherein the timing parameter includes a time between a precharge operation applied to a first bank of the memory device and a precharge operation applied to a second bank of the memory device.

77. The method of claim 68, further including:

providing power to the memory device;

after providing the power, starting a clock signal; and

providing an initialization command to the memory device after an amount of time has elapsed from starting the clock signal.

78. The method of claim 68, wherein the storage area located on the memory module is a serial presence detect device.

79. A method of operation of a memory device having an array of memory cells, the method comprising:

step for conducting initialization operations at a first frequency of operation; and

step for performing memory access operations at a second frequency of operation, wherein the second frequency is higher than the first frequency, wherein the memory access operations include a read operation and a write operation.