External data interface in a computer architecture for broadband networks

• US 20050120187A1
• Filed: 10/05/2004
• Published: 06/02/2005
• Est. Priority Date: 03/22/2001
• Status: Active Grant

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Yamazaki, Takeshi, Suzuoki, Masakazu
• Granted Patent: US 7,231,500 B2
• Time in Patent Office: Days
• US Class Current: 711/156
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G06F 12/1483 using an access-table, e.g. matrix or list
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation

Abstract

A system configuration includes a processing element (PE), an input/output (I/O) interface device and a shared memory. The PE further includes at least one processing unit (PU) and one, or more, attached processing units (APUs). At least one of the APUs performs an I/O function by reading data from, and writing data to, an external device coupled to the I/O interface device. Data is exchanged between the APU and the I/O interface device via the shared memory using a data level synchronization mechanism.

Claims

1. A system comprising:

an interface device operable to communicate data to and from an external device; and

a memory having a plurality of memory locations each operable to store the data,

at least one of the interface device and the memory being operable to store status information associated with respective ones of the memory locations, the status information including a first field and an address field, such that, for a given memory location, when a value of the first field of the associated status information equals a first value, and a value of the address field of the associated status information equals a second value, a write operation to the memory location causes data currently stored therein to be written to an address represented by the second value.

2. The system of claim 1 wherein the address is associated with the external device.

3. The system of claim 1 wherein the address is associated with a memory location associated with a processor in communication with the interface device.

4. The system of claim 1 comprising a processor coupled to the memory for data access and coupled to the interface device, the processor operable to issue requests associated with the external device.

5. The system of claim 4 wherein at least one of the requests is for reading data from the external device.

6. The system of claim 4 wherein at least one of the requests is for writing data to the external device.

7. The system of claim 4 wherein the memory is operable to pass the requests between the processor and the interface device.

8. The system of claim 1 wherein the external device is integrated with the interface device.

9. The system of claim 1 wherein the interface device communicates data between the external device and the memory using a direct memory access (DMA) transfer.

10. A system comprising:

a memory having a plurality of memory locations;

a processor coupled to the memory, the processor operable to issue a request, the request having at least one of a first type and a second type; and

an interface device operable to transfer data from an external device to the memory for storage therein in response to receiving a request having the first type, and to transfer data from storage in the memory to the external device in response to receiving a request having the second type,

wherein memory locations of at least one of the memory and the interface device support a number of different memory states including a blocking state, such that a write operation to a given memory location in the blocking state causes data currently stored therein to be written to an address value associated with the given memory location.

11. The system of claim 10 wherein the address value represents the external device.

12. The system of claim 10 further comprising a local memory associated with the processor, wherein the address value represents a memory location of the local memory.

13. The system of claim 10 wherein the first type of the request is for reading data from the external device.

14. The system of claim 10 wherein the second type of the request is for writing data to the external device.

15. The system of claim 10 wherein the external device is integrated with the interface device.

16. The system of claim 10 wherein the interface device communicates data between the external device and the memory using a direct memory access (DMA) transfer.

17. The system of claim 10 wherein the processor includes a processing unit (PU) and at least one attached processing unit (APU), wherein the attached processing unit is operable to issue the request.

18. The apparatus of claim 17 wherein the interface device includes a protection table for controlling access to ones of the memory locations.

19. The apparatus of claim 18 wherein the PU initializes values of the protection table.

20. Apparatus for interfacing between an external device and a processor, the apparatus comprising:

a protection table operable to store information indicating areas of a shared memory that are accessible by the processor;

a transfer controller responsive to a request from the processor to control a transfer of data between the external device and at least one of the accessible areas of the shared memory; and

a transfer path operable under control by the transfer controller to transfer the data between the external device and the at least one accessible area of the shared memory,

the transfer controller being operable to control the transfer the data in a synchronized manner between a memory location of the at least one accessible area and the external device according to a current memory state of the memory location, such that when the current memory state is a blocking state, a write operation to the memory location causes data currently stored in the memory location to be written to an address associated with the memory location.

21. A method for transferring data between a processor and an external device, via an interface device, the method comprising:

transferring the data between the external device and a memory local to the processor through a shared memory having a plurality of memory locations, wherein the shared memory supports a number of different memory states including a blocking state, wherein a write operation to a given memory location in the blocking state causes data currently stored therein to be written to an address value associated with the given memory location.

22. The method of claim 21, wherein the processor is a first processor, the method further comprising sending, from a second processor, to the interface device, values for use in a protection table of the interface device, wherein the values control access to portions of the shared memory.

23. The method of claim 21, further comprising, in the external device,

receiving a command by the external device, the command requesting the data to be transferred;

checking values of a protection table to determine if an address value associated with the command is valid; and

if the address value is valid, performing the initiating step.

24. The method of claim 21, wherein the associated address value represents the external device.

25. The method of claim 21, wherein the associated address value represents a local memory associated with the processor.

26. A device comprising:

a first bus for conveying a plurality of request/reply channels, each request/reply channel associated with a processor, each request/reply channel conveying requests for communicating data between the associated processor and an external device;

a second bus in data communication with a memory, for use in communicating the data using data level synchronization, the memory including a plurality of memory locations each supporting a number of different memory states including a blocking state, wherein a write operation of data to a given memory location in the blocking state causes the data currently stored in the given memory location to be written to an address value associated with the given memory location.

27. The device of claim 26 wherein the first bus conveys values for use in a protection table, the values indicating portions of the memory that are accessible by the processor.