Checkpoint-based register reclamation

• US 20050120191A1
• Filed: 12/02/2003
• Published: 06/02/2005
• Est. Priority Date: 12/02/2003
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rajwar, Ravi, Srinivasan, Srikanth T., Akkary, Haitham H.
• Application Number:
  US10/724,874
• Publication Number:
  US 20050120191A1
• Time in Patent Office: Days
• US Class Current: 712/217
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers

Abstract

A processor enabled with checkpoints may be used to recover registers using counter entry and release.

Claims

1. A method, comprising:

generating a checkpoint, wherein said checkpoint is associated with at least one physical register, and wherein said at least one physical register is associated with at least one counter;

maintaining said at least one physical register until said checkpoint is retired, wherein said at least one physical register is mapped to a logical register;

updating said at least one counter when one or more instructions are mapped to said logical register;

retiring said checkpoint when all of said one or more instructions associated with said checkpoint have completely executed; and

releasing said at least one physical register associated with said checkpoint.

2. The method of claim 1, said updating said at least one counter further comprising:

incrementing said at least one counter when at least one instruction with said logical register as an input operand is renamed to said at least one physical register.

3. The method of claim 2, said updating said at least one counter further comprising:

decrementing said at least one counter when said instruction is issued and reads said at least one physical register.

4. The method of claim 1, said releasing said at least one physical register further comprising:

releasing said at least one physical register when said counter is decremented, wherein said decrementing reaches a state indicating that none of said instructions have yet to read said at least one physical register.

5. The method of claim 4, said releasing said at least one physical register further comprising:

releasing said at least one physical register only after said associated checkpoint is released.

6. The method of claim 1, wherein said checkpoint includes at least one unmapped flag for each of said at least one physical register associated with said checkpoint.

7. The method of claim 1, wherein said at least one counter is incremented when said checkpoint is generated.

8. The method of claim 1, wherein said at least one counter is decremented when said checkpoint is retired.

9. An apparatus, comprising:

a branch predictor to generate a checkpoint, wherein said checkpoint is associated with at least one physical register;

a checkpoint buffer to maintain said at least one physical register, said at least one physical register associated with one or more instructions;

wherein said branch predictor retires said checkpoint when all of said one or more instructions have completely executed and releases said at least one physical register associated with said checkpoint.

10. The apparatus of claim 9, wherein said checkpoint buffer increments at least one counter when said checkpoint is generated;

wherein said at least one counter is associated with said at least one physical register.

11. The apparatus of claim 9, wherein said checkpoint buffer decrements at least one counter when said checkpoint is retired, wherein said at least one counter is associated with said at least one physical register.

12. The apparatus of claim 9, wherein said branch predictor increments at least one counter when at least one of said one or more instructions with a logical register as an input operand is renamed to said at least one physical register.

13. The apparatus of claim 9, wherein said branch predictor decrements at least one counter when at least one of said one or more instructions is issued and reads said at least one physical register.

14. The apparatus of claim 9, wherein said branch predictor releases said at least one physical register when at least one counter is decremented to a state indicating that none of said one or more instructions have yet to read said at least one physical register.

15. The apparatus of claim 14, wherein said branch predictor releases said at least one physical register after said checkpoint is released.

16. The apparatus of claim 9, wherein said checkpoint includes at least one unmapped flag for each of said at least one physical registers associated with said checkpoint.

17. A system, comprising:

a processor including a branch predictor to a branch predictor to generate a checkpoint, wherein said checkpoint is associated with at least one physical register, a checkpoint buffer to maintain said at least one physical register, said at least one physical register associated with one or more instructions, wherein said branch predictor retires said checkpoint when all of said one or more instructions have completely executed and releases said at least one physical register associated with said checkpoint;

an interface to couple said processor to input-output devices; and

a data storage coupled to said interface to receive code from said processor.

18. The system of claim 17, wherein said checkpoint buffer increments at least one counter when said checkpoint is generated;

wherein said at least one counter is associated with said at least one physical register.

19. The system of claim 17, wherein said checkpoint buffer decrements at least one counter when said checkpoint is retired, wherein said at least one counter is associated with said at least one physical register.

20. The system of claim 17, wherein said branch predictor increments at least one counter when at least one of said one or more instructions with a logical register as an input operand is renamed to said at least one physical register.

21. The system of claim 17, wherein said branch predictor decrements at least one counter when at least one of said one or more instructions is issued and reads said at least one physical register.

22. The system of claim 17, wherein said branch predictor releases said at least one physical register when at least one counter is decremented to a state indicating that none of said one or more instructions have yet to read said at least one physical register.

23. The system of claim 22, wherein said branch predictor releases said at least one physical register after said checkpoint is released.

24. The system of claim 17, wherein said checkpoint includes at least one unmapped flag for each of said at least one physical registers associated with said checkpoint.