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System and method for testing a memory using DMA

  • US 20050120268A1
  • Filed: 11/14/2003
  • Published: 06/02/2005
  • Est. Priority Date: 11/14/2003
  • Status: Active Grant
First Claim
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1. A computer system comprising:

  • a processor;

    a first bus coupled to the processor;

    a memory controller coupled to the first bus;

    a memory coupled to the memory controller;

    a first input/output (I/O) controller coupled to the first bus; and

    a test module coupled to the first I/O controller;

    wherein the test module is configured to cause tests to be performed on the memory using the first bus.

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