Apparatus and method for performing speculative reads from a scan control unit using FIFO buffer units

• US 20050120269A1
• Filed: 09/16/2004
• Published: 06/02/2005
• Est. Priority Date: 11/05/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Larson, Lee A., Hoar, Henry R.
• Granted Patent: US 7,437,623 B2
• Time in Patent Office: Days
• US Class Current: 714/29
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

In a JTAG test and debug environment, the signal groups may have a variable length, a fixed length of a combination of both fixed and variable signal groups to be transferred to the target processor. To implement the three types of data transfers, the storage unit associated with the scan control unit includes two types of storage locations, fixed signal length storage locations and variable length storage locations. The software can select the mode of data transfer and this selection is provided to the scan controller by a command.

Claims

1. A test and debug system for testing a target processor, the system comprising:

data transfer apparatus in the target processor to receiving data and for transferring data;

a test access port in the target processor responsive to control signals, the control signals determining the state of the test and debug apparatus in the target processor; and

a scan control unit, the scan control unit including;

a processor responsive to commands for generating the control signals;

at least one register responsive to signals from the processor for exchanging data with the data transfer apparatus; and

a storage unit having at least one fixed length location and at least one variable length storage location.

2. The system as recited in claim 1 wherein the scan control unit can transfer to the target processor fixed length signal groups, variable length signal groups, or signal groups having both fixed signal group and variable signal group components.

3. The system as recited in claim 2 wherein, in response to a command from the test and debug processing unit, mode of signal group transfer identified by parameters of the command is implemented.

4. The system as recited in claim 3 wherein the signal group is boundary scan signal group.

5. In a JTAG test and debug system, a method for transferring signal groups under the control of a scan control unit, the method comprising:

storing the signal group in at least one of a fixed signal group length register and a variable length signal group storage locations; and

in response to command, transferring the signal group to a target processor in a fixed signal group mode, a variable signal group mode or mixed signal group mode.

6. The method as recited in claim 5 wherein the signal group is a boundary scan signal group.

7. In a test and debug unit, a scan control unit comprising:

a local processor responsive to at least one command;

a shift register out, the shift register out shifting signals out of the scan control unit; and

a storage unit having fixed signal group length storage locations and at least one variable signal group storage location.

8. The scan control unit as recited in claim 7 wherein the local processor, in response to a parameter in a command, shifts the stored signal groups in a fixed mode, in a variable mode, or in both modes.

9. The scan control unit as recited in claim 8 wherein the signal group is a boundary scan signal group.