Battery activation circuit

• US 20050121526A1
• Filed: 12/08/2004
• Published: 06/09/2005
• Est. Priority Date: 12/09/2003
• Status: Active Grant

• Current Assignee: Zest Labs, Inc.
• Original Assignee: Intelleflex Corporation
• Inventors: Paley, Daniel Noah, Stewart, Roger Green
• Granted Patent: US 7,612,652 B2
• Time in Patent Office: Days
• US Class Current: 235/492
• CPC Class Codes: G06K 19/0705 the battery being connected to a power saving arrangement
• CPC Class Codes: G06K 19/0707 the arrangement being capable of collecting energy from external energy sources, e.g. thermocouples, vibration, electromagnetic radiation G06K19/0702 takes precedence
• CPC Class Codes: G06K 19/0712 the arrangement being capable of triggering distinct operating modes or functions dependent on the strength of an energy or interrogation field in the proximity of the record carrier active means for hindering electromagnetic reading or writing G06K19/07336
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

A system and method for selectively activating a device based on an activate command. A circuit, in low power mode, listens for an activate command. The activate command includes a preamplifer centering sequence, an interrupt signal, and an activate code. The circuit receives a signal that may or may not be an activate command, self-biases the signal based on the preamplifer centering in the preamp/gain control, then determines whether the interrupt signal is of the proper length in the interrupt circuit. If the interrupt is not the proper length, the process stops. If it is the proper length, the command is recognized as an activate command, and a data slicer compares the activate code to a prestored value. If the activate code matches the prestored value, the device is powered up. If they do not match, the device is not initiated.

Claims

1. A circuit for activating a device, comprising:

an interrupt circuit for determining whether an interrupt period of a received signal matches a predetermined plurality of values or falls within a predetermined range, the interrupt circuit outputting an interrupt signal if the interrupt period matches the predetermined value or falls within the predetermined range; and

a data slicer for comparing a received activate code to a stored value, the data slicer sending a wake up signal for activating the device if the received activate code matches the stored value.

2. A circuit as recited in claim 1, wherein the circuit is implemented in a radio frequency identification (RFID) tag.

3. A circuit as recited in claim 1, further comprising a self-biasing amplifier that sets a bias point based on a 50% duty cycle waveform of a received preamplifer centering sequence.

4. A circuit as recited in claim 1, further comprising a band pass filter for excluding unwanted noise from a received signal.

5. A circuit as recited in claim 1, wherein the interrupt circuit includes a five input logic gate.

6. A circuit as recited in claim 1, wherein the interrupt circuit includes:

a first pair of mirror inverters, each inverter being tuned for a different specified delay timing, the first pair of mirror inverters detecting whether a low period of an interrupt pulse is between the specified delay timings;

a second pair of mirror inverters, each inverter being tuned for a different specified delay timing, the second pair of mirror inverters detecting whether a high period of the interrupt pulse is between the specified delay timings;

a first latch sampling and storing output from the first pair of mirror inverters;

a second latch sampling and storing output from the second pair of mirror inverters;

a third latch sampling and storing output from the first latch; and

a logic gate receiving output from the second latch and output from the third latch,

wherein output from the logic gate is the interrupt signal.

7. A circuit as recited in claim 6, further comprising a first exclusive OR (XOR) gate positioned between the first pair of mirror inverters and the first latch, and a second XOR gate positioned between the second pair of mirror inverters and the second latch, wherein output of the first XOR gate is activated if the low period of the interrupt pulse is between the specified delay times of the first pair of mirror inverters, wherein output of the second XOR gate is activated if the high period of the interrupt pulse is between the specified delay times of the second pair of mirror inverters.

8. A circuit as recited in claim 6, further comprising a series of inverters between the first pair of mirror inverters and the third latch.

9. A circuit as recited in claim 6, further comprising a series of inverters between the second pair of mirror inverters and the second latch.

10. A circuit as recited in claim 6, wherein the latches include pass gates.

11. A circuit as recited in claim 6, wherein the logic gate also receives output from a feedback latch storing a value associated with the interrupt pulse.

12. A circuit as recited in claim 1, further comprising an an adaptive timing circuit for controlling the data slicer.

13. A circuit as recited in claim 1, further comprising adaptive timing circuit for enabling and adjusting a clock for subsequent processing, wherein an output value of the adaptive timing circuit is stored in a latch, wherein the adaptive timing circuit is powered down upon storing the output value of the adaptive timing circuit in the latch.

14. A circuit as recited in claim 1, wherein the received signal is an activate command having a preamplifer centering sequence, the interrupt period, and the activate code.

15. A circuit for activating a device, comprising:

an interrupt circuit for determining whether an interrupt period of a received signal matches a predetermined plurality of values or falls within a predetermined range, the interrupt circuit outputting an interrupt signal if the interrupt period matches the predetermined value or falls within the predetermined range;

an adaptive timing circuit receiving the interrupt signal from the interrupt circuit, the adaptive timing circuit enabling and adjusting a clock for subsequent processing; and

a calibrator for tuning the adaptive timing circuit.

16. A circuit as recited in claim 15, further comprising a data slicer for comparing a received activate code to a stored value, the data slicer sending a wake up signal for activating the device if the received activate code matches the stored value.

17. A circuit for identifying an interrupt, comprising:

a first pair of mirror inverters, each inverter being tuned for a different specified delay timing, the first pair of mirror inverters detecting whether a low period of an interrupt pulse is between the specified delay timings;

a second pair of mirror inverters, each inverter being tuned for a different specified delay timing, the second pair of mirror inverters detecting whether a high period of the interrupt pulse is between the specified delay timings;

a first latch sampling and storing output from the first pair of mirror inverters;

a second latch sampling and storing output from the second pair of mirror inverters;

a third latch sampling and storing output from the first latch; and

a logic gate receiving output from the second latch and output from the third latch,

wherein output from the logic gate is indicative of a successful identification of an interrupt.

18. A circuit as recited in claim 17, further comprising a first exclusive OR (XOR) gate positioned between the first pair of mirror inverters and the first latch, and a second XOR gate positioned between the second pair of mirror inverters and the second latch, wherein output of the first XOR gate is activated if the low period of the interrupt pulse is between the specified delay times of the first pair of mirror inverters, wherein output of the second XOR gate is activated if the high period of the interrupt pulse is between the specified delay times of the second pair of mirror inverters.

19. A circuit as recited in claim 17, wherein the circuit is implemented in a radio frequency identification (RFID) tag.

20. A circuit as recited in claim 17, wherein the latches include pass gates.

21. A circuit as recited in claim 17, wherein the logic gate also receives output from a feedback latch storing a value associated with the interrupt pulse.

22. A circuit as recited in claim 17, further comprising a series of inverters between the first pair of mirror inverters and the third latch.

23. A circuit as recited in claim 17, further comprising a series of inverters between the second pair of mirror inverters and the second latch.

24. A method for activating a device, comprising:

listening for an activate command at a device;

receiving the activate command, the activate command including a preamplifer centering sequence, an interrupt period, and an activate code;

analyzing the activate code if the interrupt period matches a predetermined value or falls within a predetermined range; and

activating the device if the activate code matches a value stored in the device.

25. A method as recited in claim 24, wherein the method is implemented in a radio frequency identification (RFID) tag.

26. A method as recited in claim 24, wherein the method is performed by several RFID tags, several of the tags being activated upon receiving a particular activate command.

27. A method as recited in claim 24, wherein the method is implemented in multiple devices.

28. A method as recited in claim 24, wherein one particular activate code instructs the device to respond to all querying devices.

29. A method as recited in claim 24, wherein the device responds to multiple activate codes.

30. A method as recited in claim 24, wherein the preamplifer centering sequence is a 50% duty cycle waveform.

31. A method as recited in claim 24, wherein an interrupt circuit is used to determine whether the interrupt period matches the predetermined value or falls within the predetermined range, the interrupt circuit comprising:

a first pair of mirror inverters, each inverter being tuned for a different specified delay timing, the first pair of mirror inverters detecting whether a low period of an interrupt pulse is between the specified delay timings;

a second pair of mirror inverters, each inverter being tuned for a different specified delay timing, the second pair of mirror inverters detecting whether a high period of the interrupt pulse is between the specified delay timings;

a first latch sampling and storing output from the first pair of mirror inverters;

a second latch sampling and storing output from the second pair of mirror inverters;

a third latch sampling and storing output from the first latch; and

a logic gate receiving output from the second latch and output from the third latch,

wherein output from the logic gate is the interrupt signal.

32. A method as recited in claim 31, wherein the logic gate also receives output from a feedback latch storing a value associated with the interrupt pulse.

33. A method for activating a device using an activate code, comprising:

receiving an activate code at a device;

comparing the activate code to a prestored value;

activating the device if the activate code matches the prestored value; and

not activating the device if the activate code does not match the prestored value.

34. A method as recited in claim 33, wherein the method is implemented in a radio frequency identification (RFID) tag.

35. A method as recited in claim 33, wherein the method is performed by several RFID tags, several of the tags being activated upon receiving a particular activate code.

36. A method as recited in claim 33, wherein the method is performed by several RFID tags, the tags responding to multiple readers upon receiving a particular activate code.

37. A method as recited in claim 33, wherein one particular activate code activates all devices.

38. A method as recited in claim 33, wherein one particular activate code bypasses the activate circuit.

39. A method as recited in claim 33, further comprising synchronizing a clock and recognizing an interrupt period indicative of an activate command, wherein the activate code being received as part of the activate command.

40. A method as recited in claim 33, wherein an activate circuit compares the activate code to the prestored value and activates the device if the activate code matches the prestored value.

41. A method as recited in claim 33, wherein the activate code is part of an activate command, the activate command further including a preamplifer centering sequence and an interrupt period, the activate code not being compared to the prestored value unless the interrupt period falls within a prespecified range.

42. A method as recited in claim 33, wherein the activate code is received as part of a string of data symbols, wherein only two types of symbol signals are present in the string of data symbols.

43. A method for activating a device using an activate code, comprising:

receiving a string of symbols;

attempting to recognize a symbol or combination of symbols as an interrupt;

comparing a sequence of symbols received subsequent to a recognized interrupt to a prestored value;

activating at least a portion of the device if the sequence of symbols received subsequent to the interrupt matches the prestored value; and

not activating the at least a portion the device if the sequence of symbols received subsequent to the interrupt do not match the prestored value.

44. A method as recited in claim 43, further comprising stopping the comparing and repeating the method upon determining that a symbol in the sequence does not match the prestored value.

45. A method as recited in claim 43, wherein only two types of symbol signals are present in the string of symbols.

46. A method as recited in claim 43, wherein the string of symbols is asynchronous.

47. A method as recited in claim 46, wherein only two types of symbol signals are present in the string of symbols, wherein a first type of the symbol signals have four times the duration as a second type of the symbol signals.

48. A method for activating a plurality of selected devices, comprising:

sending multiple different activate commands to remote devices, each remote device analyzing the activate commands to determine whether one of the activate commands includes an activate code matching a value stored on the particular device; and

activating the device if one of the activate codes matches a value stored in the device.

49. A method as recited in claim 48, further comprising communicating with the activated devices simultaneously.

50. A method for activating a plurality of selected devices, comprising:

receiving a data stream with a sequence of data symbols;

detecting a particular symbol cluster from within the data stream;

wherein the symbol cluster identifies a data sequence of interest in the data stream,

wherein the symbol is comprised of two or more symbols,

wherein the symbol cluster is not present in the data sequence of interest for preserving an identifying characteristic of the symbol cluster.

51. A method as recited in claim 50, wherein the symbol cluster is an interrupt.

52. A method as recited in claim 50, wherein the symbol cluster initiates a start of comparison of a subsequent data stream.

53. A method as recited in claim 50, wherein the data sequence of interest is an activate code.

54. A method as recited in claim 50, wherein the symbols in the data stream are based on two symbol types having a relationship based on a durational interval, wherein one of the symbol types is a fraction of the duration of the other symbol type, wherein sufficient differentiation between the symbols exists to distinguish one symbol type from the other symbol type.

55. A method for encoding data using durational parameters, comprising:

generating a data stream having two symbol types having a relationship based on a durational interval, wherein one of the symbol types is a fraction of the duration of the other symbol type, wherein sufficient differentiation between the symbols exists to distinguish one symbol type from the other symbol type.

56. A method as recited in claim 55, wherein the fractional relationship is a whole number.

57. A method as recited in claim 55, wherein the fractional relationship is not a whole number.