Gapped-plate capacitor

• US 20050121740A1
• Filed: 01/18/2005
• Published: 06/09/2005
• Est. Priority Date: 09/03/1998
• Status: Active Grant

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: David Y. Kao, James Peacher
• Inventors: Kao, David Y., Peacher, James
• Granted Patent: US 7,151,659 B2
• Time in Patent Office: Days
• US Class Current: 257/528
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS

Abstract

In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

Claims

1-31. -31. (canceled)

32. A storage device, comprising:

an oxide layer;

a bottom electrode under said oxide layer; and

a top plate over said oxide layer and further comprising;

a first portion over said bottom electrode and defining a first cavity.

33. The storage device in claim 32, wherein said top plate further comprises a second portion defining a second cavity.

34. The storage device in claim 33, wherein:

said first cavity is a slit; and

said second cavity is a slit and intersects said first cavity.

35. The storage device in claim 34, wherein said second cavity intersects said first cavity at an angle of generally 90 degrees.

36. The storage device in claim 34, wherein said top plate defines:

a first plurality of slits; and

a second plurality of slits intersecting said first plurality of slits.

37. A capacitor, comprising:

a substrate;

a patterned conductive layer over said substrate, including a first hole;

an oxide between said substrate and said patterned conductive layer and within said first hole.

38. The capacitor in claim 37, wherein said patterned conductive layer has a second hole shaped differently from said first hole.

39-53. -53. (canceled)

54. A capacitor, comprising:

a first electrically conductive plate having a first portion;

a second electrically conductive plate, further comprising;

a second portion generally parallel to said first portion of said first electrically conductive plate and configured to allow for parallel capacitance in cooperation with said first electrically conductive plate, and

a third portion defining a primary slot within said second electrically conductive plate and configured to allow for fringe capacitance in cooperation with said first portion of said first electrically conductive plate, wherein said fringe capacitance is at least equal to said parallel capacitance per a unit of measurement; and

a dielectric between said first electrically conductive plate and said second electrically conductive plate and within said primary slot.

55. The capacitor in claim 54, wherein said second electrically conductive plate is under said first electrically conductive plate.

56. The capacitor in claim 55, wherein said second electrically conductive plate further comprises a substrate.

57. The capacitor in claim 56, wherein said first electrically conductive plate further comprises a fourth portion defining a secondary slot within said first electrically conductive plate and configured to allow for fringe capacitance in cooperation with said second electrically conductive plate that is at least equal to said parallel capacitance per said unit of measurement.

58. The capacitor in claim 57, wherein said primary slot defines an axis generally perpendicular to said first portion of said first electrically conductive plate.

59. A semiconductor device, comprising:

a substrate;

an oxide over said substrate; and

a conductive layer over said oxide, wherein said conductive layer and said substrate are configured to generate a parallel capacitance, and wherein a selection of said substrate and said conductive layer is untextured and defines a gap associated with a fringe capacitance that is at least as great as said parallel capacitance per a unit of width.

60. The semiconductor device in claim 59, wherein said substrate is generally free of microstructures and defines said gap.

61. A capacitor, comprising:

a first electrode;

a second electrode defining an opening separate from said first electrode; and

a dielectric between said first electrode and said second electrode.

62. (canceled)

63. A capacitor, comprising:

a dielectric layer;

a first plate on one side of said dielectric layer; and

a second plate on another side of said dielectric layer and defining a generally continuous surface and a discontinuity at said surface, wherein said surface is configured to generate parallel capacitance with said first plate and said discontinuity is configured to generate fringe capacitance with said first plate.

64. The capacitor in claim 63, wherein:

said first plate is planar;

said generally continuous surface is a planar surface parallel to said first plate; and

said discontinuity is nonparallel to said first plate.

65. The capacitor in claim 64, wherein said discontinuity is vertically offset from said first plate.

66. The capacitor in claim 65, wherein said discontinuity is perpendicular to said first plate.

67-110. -110. (canceled)