Programmable structured arrays

• US 20050121789A1
• Filed: 12/04/2003
• Published: 06/09/2005
• Est. Priority Date: 12/04/2003
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Raminda Udaya Madurawe
• Inventors: Madurawe, Raminda Udaya
• Granted Patent: US 7,030,651 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/1733 Controllable logic circuits H03K19/177 takes precedence
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/18 Peripheral circuit regions
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A programmable wire structure for an integrated circuit, comprising: a programmable switch coupling two nodes, said switch having a first state that connects said two nodes, and said switch having a second state that disconnects said two nodes; and a configuration circuit coupled to said programmable switch, said circuit comprising a means to program said switch between said first and second state; and a first metal layer fabricated above a silicon substrate layer, said switch and said configuration circuit fabricated substantially above said first metal layer. A semiconductor device for integrated circuits with two selectable manufacturing configurations, comprising: a first module layer having an array of structured cells, said module layer having at least one layer of metal; and a second module layer formed substantially above said first module layer comprising two selectable configurations, wherein: in a first selectable configuration a programmable interconnect structure is formed to connect said structured cells, and in a second selectable configuration a customized interconnect structure is formed to connect said structured cells.

Claims

1. A programmable wire structure for an integrated circuit, comprising:

a programmable switch coupling two nodes, said switch having a first state that connects said two nodes, and said switch having a second state that disconnects said two nodes; and

a configuration circuit coupled to said programmable switch, said circuit comprising a means to program said switch between said first and second state; and

a first metal layer fabricated above a silicon substrate layer, said switch and said configuration circuit fabricated substantially above said first metal layer.

2. The structure of claim 1, wherein a second metal layer is fabricated substantially above said switch and said configuration circuit

3. The structure of claim 1, wherein at least one of said first and second nodes is coupled to a node in said first metal.

4. The structure of claim 2, wherein at least one of said first and second nodes is coupled to a node in said second metal.

5. The structure of claim 1, wherein said programmable switch comprises a thin film transistor.

6. The structure of claim 5, wherein at least one of said first and second nodes of said programmable switch further comprises a via structure, said via structure containing a seed metal, said seed metal facilitating a thermally activated phase change of at least one of said thin film materials to improve conduction of said connect state.

7. The structure of claim 1, wherein said configuration circuit comprises a thin film transistor.

8. The device of claim 1, wherein said configuration circuit comprises a memory element.

9. The structure of claim 8, wherein said memory element is selected from one of fuse links, anti-fuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, flash cells, ferro-electric elements, electrochemical elements, optical elements and magnetic elements.

10. The structure of claim 8, wherein the programmable means further comprises:

a pass-gate device, said pass-gate controlled by an output signal from said memory element, said first state generated by an on pass-gate, and said second state generated by an off pass-gate; and

a configuration access to program said memory data, said memory bit polarity generating an on and off control signal to select said state of pass-gate device.

11. A wire structure for an integrated circuit having two selectable methods of connecting wires, comprising:

a first selectable method comprising programmable switches, each said switch coupling a wire in a first set to a wire in a second set, and said method providing a means to program a user defined interconnect pattern between said first and second set of wires; and

a second selectable method comprising permanent connections in lieu of said switches, said permanent connection pattern duplicating one of said user defined interconnect patterns.

12. The structure of claim 11, wherein said programmable switch is comprised one of a thin film diode, thin film resistor, thin film capacitor and a thin film transistor.

13. The structure of claim 11, wherein said programmable switch is comprised one of a volatile and a non volatile memory element.

14. The structure of claim 13, wherein said memory element is selected from one of fuse links, anti-fuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, flash cells, ferro-electric elements, electrochemical elements, optical elements and magnetic elements.

15. The structure of claim 11, wherein said second selectable method further comprises fabricating permanent connections using at least one of a customized metal mask and a customized through-hole mask.

16. The structure of claim 11, wherein said programmable switch further comprises:

one or more connecting devices, each of said devices comprising a connect-state and a disconnect-state, said device coupling a wire in said first set and a wire in said second set; and

a configuration circuit comprising one or more memory elements, each said memory element generating a control signal, said signal comprising a logic-low and a logic-high level, said signal further coupled to one or more of said connecting devices; and

a programmable means of changing data in said memory elements, said change altering said control signal level, said level further altering said connecting device state.

17. The structure of claim 11, said first selectable method is further comprised of:

fabricating an array of programmable cells on a substrate layer; and

fabricating one or more pass-gates on thin-film layers substantially above said substrate layer, each said pass-gate connecting a wire in said first set to a wire in said second set; and

fabricating configuration access transistors and memory elements on said thin-film layers, each said memory element generating a control signal; and

coupling said control signal from each of said thin film memory elements to a gate electrodes of said pass-gates; and

providing programmable access to change said thin film memory data via said thin film access transistors.

18. A semiconductor device for integrated circuits with two selectable manufacturing configurations, comprising:

a first module layer having an array of structured cells, said module layer having at least one layer of metal; and

a second module layer formed substantially above said first module layer comprising two selectable configurations, wherein;

in a first selectable configuration a programmable interconnect structure is formed to connect said structured cells, and

in a second selectable configuration a customized interconnect structure is formed to connect said structured cells.

19. The device of claim 18, further comprising a third module layer formed substantially above said second module layer comprised of a plurality of metal layers, said metal layers providing conductive wires to complete interconnect and routing of said semiconductor device.

20. The device of claim 18, further comprising:

each said structured cell comprising inputs and outputs, said inputs and outputs formed in said first module layer; and

a portion of said inputs and outputs requiring one of said selectable second modules to connect to each other.

21. The device of claim 18, further comprising:

said first selectable configuration comprised of a plurality of programmable interconnect patterns, a unique said pattern programmed by a user; and

said second selectable configuration comprised of an interconnect pattern duplicating said unique programmed pattern; and

said array of structured cells comprising an interconnect pattern, said interconnect pattern identical with either of said selectable options.

22. The device of claim 18, wherein said programmable interconnect structure is further comprised of a user configurable memory circuit constructed on a thin film layer comprising one of fuse links, anti-fuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, flash cells, ferro-electric elements, electro-chemical elements, optical elements and magnetic elements.

23. The method of claim 22, further comprised of said conductive pattern comprising fabricating hard wire controls to replicate a specific memory pattern, wherein replicating comprises:

a logic zero memory output mapped to a hard wire disconnect; and

a logic one memory output mapped to a hard wire connect.