Class D amplifier

• US 20050122169A1
• Filed: 11/29/2004
• Published: 06/09/2005
• Est. Priority Date: 12/01/2003
• Status: Active Grant

• Current Assignee: Nippon Precision Circuits, Inc. (Seiko Group)
• Original Assignee: Nippon Precision Circuits, Inc. (Seiko Group)
• Inventors: Watanabe, Shinichi
• Granted Patent: US 7,102,432 B2
• Time in Patent Office: Days
• US Class Current: 330/251
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers

Abstract

A class D amplifier capable of compressing a dynamic range and reproduction by changing on a real time basis a modulation ratio to a non-linear ratio in accordance with amplitude of an input signal. The class D amplifier including a triangular waveform generation circuit that generates a deformed triangular waveform used as a comparison waveform for amplitude modulating an analog input signal, the triangular waveform generation circuit comprising a pulse generation circuit for generating a plurality of first pulse signals, a plurality of pulse extraction circuit for extracting said first pulse signals selectively, and for outputting second pulse signals during the time according to extracted first pulse signals, a plurality of three state buffers to which a clock pulse signal for basic cycles is provided as an input signal, one of said second pulse signals is provided as a control signal, and said clock pulse signal for basic cycles is output during a period for said one of second pulse signal is provided, and a integration circuit, having a time constant thereof changing in accordance with the output of said three state buffer, for generating said deformed triangular waveform corresponding to the time constant based on the clock pulse signal for basic cycles.

Claims

1. A class D amplifier including a triangular waveform generation circuit that generates a deformed triangular waveform used as a comparison waveform for amplitude modulating an analog input signal, the triangular waveform generation circuit comprising:

a pulse generation circuit for generating a plurality of first pulse signals;

a plurality of pulse extraction circuit for extracting said first pulse signals selectively, and for outputting second pulse signals during the time according to extracted first pulse signals;

a plurality of three state buffers to which a clock pulse signal for basic cycles is provided as an input signal, one of said second pulse signals is provided as a control signal, and said clock pulse signal for basic cycles is output during a period for said one of second pulse signal is provided; and

a integration circuit, having a time constant thereof changing in accordance with the output of said three state buffer, for generating said deformed triangular waveform corresponding to the time constant based on the clock pulse signal for basic cycles.

2. A class D amplifier according to claim 1, further comprising:

a plurality of toggle flip flop circuits which are connected in series, for generating said clock pulse signal for basic cycles based on an externally-provided clock signal.

3. A class D amplifier according to claim 1, wherein said pulse generation circuit comprising:

a ring counter including a plurality of delay flip flop circuits which are connected in series.

4. A class D amplifier according to claim 3, wherein each of said pulse extraction circuits comprising:

a 4-NAND gate circuit to which four outputs chosen from among outputs of said delay flip flop circuits are inputted.

5. A class D amplifier according to claim 3, wherein each of said pulse extraction circuits comprising:

a 2-NAND gate circuit to which two outputs chosen from among outputs of said delay flip flop circuits are inputted.

6. A class D amplifier according to claim 1, wherein said integration circuit comprising:

an operational amplifier having a positive phase input terminal for receiving a middle point potential half level of a power source voltage of the class D amplifier, and a opposite phase input terminal for receiving said clock pulse signal for basic cycles via a first resistor, and output terminal;

a feedback capacitance interposed between said opposite phase input terminal and said output terminal of said operational amplifier; and

a second resistor interposed between said opposite phase input terminal and an output of given 3-state buffer.

a third resistor interposed between an output said three state buffer and an output other 3-state buffer.

7. A class D amplifier according to claim 6, wherein a resistance value of said first resistor, second resistor and third resistor is set to be equal.

8. A class D amplifier according to claim 1, wherein said integration circuit comprising:

an operational amplifier having a positive phase input terminal for receiving a middle point potential half level of a power source voltage of the class D amplifier, and a opposite phase input terminal for receiving said clock pulse signal for basic cycles via a first resistor, and output terminal;

a feedback capacitance interposed between said opposite phase input terminal and said output terminal of said operational amplifier; and

a second resistor interposed between said opposite phase input terminal and an output of given 3-state buffer.

a third resistor interposed between said opposite phase input terminal and an output of other 3-state buffer.

9. A class D amplifier according to claim 1, further comprising:

a sample-and-hold circuit for generating a sample-and-hold waveform based on a input signal;

a comparator for generating an amplitude modulated pulse signal of said input signal based on said sample-and-hold waveform and said deformed triangular waveform of said triangular waveform generation circuit;

a current buffer for buffering said amplitude modulated pulse signal; and

a low-pass filter for filtering an output of said current buffer.