Oscillator circuit

• US 20050122178A1
• Filed: 11/23/2004
• Published: 06/09/2005
• Est. Priority Date: 11/25/2003
• Status: Active Grant

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Goto, Kensuke
• Granted Patent: US 7,129,796 B2
• Time in Patent Office: Days
• US Class Current: 331/57
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

The ring oscillator circuit with the current mirror type current limit circuit of this invention prevents the malfunction and the halt of the ring oscillator. The ring oscillator is configured with the serially connected CMOS inverters INV1-INV5 where the output of the last CMOS inverter INV5 is fed back to the input of the first CMOS inverter INV1. Also, the current mirror type current limit circuit for controlling the electric current going through the CMOS inverters INV1-INV5 is formed. The first supporting transistor T1 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the power supply voltage Vdd and the second supporting transistor T2 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the ground voltage Vss according to the output of the CMOS inverter INV3 two positions ahead of the last inverter INV5 are also formed.

Claims

1. An oscillator circuit comprising:

a ring oscillator comprising a plurality of inverters of an odd number, the inverters being connected serially, and an output of the last inverter of the odd number of the inverters being fed back as an input to the first of the odd number of the inverters;

a current limit circuit of current mirror type controlling a current supplied to the odd number of the inverters; and

a supporting transistor receiving an output of one of the inverters that is located at an even numbered position from the last inverter so as to make the output of the last inverter swing between a power supply voltage and a reference voltage.

2. The oscillator circuit of claim 1, wherein the supporting transistor comprises a first P-channel type MOS transistor.

3. The oscillator circuit of claim 2, wherein the output of the inverter located at the even-numbered position is applied to a gate of the first P-channel type MOS transistor, the power supply voltage is applied to a source of the first P-channel type MOS transistor, and a drain of the first P-channel type MOS transistor is connected to a source of a second P-channel type MOS transistor that is part of the last inverter.

4. The oscillator circuit of claim 1, wherein the supporting transistor comprises a first N-channel type MOS transistor.

5. The oscillator circuit of claim 4, wherein the output of the inverter located at the even-numbered position is applied to a gate of the first N-channel type MOS transistor, the reference voltage is applied to a source of the first N-channel type MOS transistor, and a drain of the first N-channel type MOS transistor is connected to a source of a second N-channel type MOS transistor that is part of the last inverter.

6. An oscillator circuit comprising:

a ring oscillator comprising a plurality of inverters of an odd number, the inverters being connected serially, and an output of the last inverter of the odd number of the inverters being fed back as an input to the first of the odd number of the inverters;

a current limit circuit of current mirror type controlling a current supplied to the odd number of the inverters;

a first P-channel type MOS transistor; and

a first N-channel type MOS transistor, wherein

an output of one of the inverters that is located at an even-numbered position from the last inverter is applied to a gate of the first P-channel type MOS transistor, a power supply voltage is applied to a source of the first P-channel type MOS transistor, and a drain of the first P-channel type MOS transistor is connected to a source of a second P-channel type MOS transistor that is part of the last inverter, and

the output of the inverter located at the even-numbered position is applied to a gate of the first N-channel type MOS transistor, a reference voltage is applied to a source of the first N-channel type MOS transistor, and a drain of the first N-channel type MOS transistor is connected to a source of a second N-channel type MOS transistor that is part of the last inverter.