Video, audio and graphics decode, composite and display system

• US 20050122335A1
• Filed: 11/23/2004
• Published: 06/09/2005
• Est. Priority Date: 11/09/1998
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander G., Cheung, Francis, Hsiun, Vivian, Tang, Chengfuh Jeffrey, Bhatia, Sandeep, Kranawetter, Greg A., Xie, Xiaodong, Valmiki, Ramanujan, Kumar, Sathish
• Granted Patent: US 7,110,006 B2
• Time in Patent Office: Days
• US Class Current: 345/520
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2350/00 Solving problems of bandwidth in display systems
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 : Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 : Graphics controllers
• CPC Class Codes: H04L 12/28 : characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks] wireless communication networks H04W ; arrangements for dividing the transmission path H04W40/00
• CPC Class Codes: H04N 11/00 : Colour television systems details H04N9/00
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 11/22 : in which simultaneous signals are converted into sequential signals or vice versa
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/42692 : for reading from or writing on a volatile storage medium, e.g. Random Access Memory [RAM]
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/4345 : Extraction or processing of SI, e.g. extracting service information from an MPEG stream
• CPC Class Codes: H04N 21/4348 : Demultiplexing of additional data and video streams
• CPC Class Codes: H04N 21/440218 : by transcoding between formats or standards, e.g. from MPEG-2 to MPEG-4 conversion of standards in analogue television systems H04N7/01
• CPC Class Codes: H04N 21/4435 : Memory management allocation of memory to service a request G06F9/5016; addressing or allocating within memory systems or architectures G06F12/02
• CPC Class Codes: H04N 21/8146 : involving graphical data, e.g. 3D object, 2D graphics
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence

Abstract

A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.

Claims

1. An integrated circuit comprising:

an input for receiving analog video;

an input for receiving data representing graphics;

an input for receiving a plurality of compressed data streams, the compressed data streams including video data;

an analog video decoder for decoding the analog video to generate digitized analog video;

a display engine for blending the data representing graphics to generate blended graphics;

a digital video decoder for processing the video data to generate decoded video data; and

a video compositor for blending the digitized analog video, the blended graphics and the decoded video data to provide an output of blended video and graphics.

2. The integrated circuit of claim 1 wherein the plurality of compressed data streams include one or more MPEG Transport streams.

4. The integrated circuit of claim 1 wherein the video data include HDTV video data.

5. The integrated circuit of claim 1 wherein the video data include SDTV video data.

6. The integrated circuit of claim 1 further comprising a system bridge controller for coupling a CPU to one or more peripheral devices.

7. The integrated circuit of claim 6 wherein the one or more peripheral devices include one or more PCI devices, and wherein the system bridge controller includes a PCI bridge to couple the CPU to the one or more PCI devices.

10. The integrated circuit of claim 1 wherein the plurality of compressed data streams further include audio data, and the integrated circuit further comprises an audio decode processor for decoding the audio data.

11. The integrated circuit of claim 1 wherein at least one of the plurality of compressed data streams include data other than the video data or audio data.

12. The integrated circuit of claim 1 further comprising a core transport processor for accepting or rejecting data packets from the plurality of compressed data streams based on the value of a packet identification field of each data packet.

14. The integrated circuit of claim 12 wherein one or more of the plurality of compressed data streams include encrypted data, and the core transport processor decrypts the encrypted data.

15. The integrated circuit of claim 2 wherein the video data include MPEG video data included in at least one MPEG Transport stream, and the integrated circuit further comprises a satellite transport processor to extract the MPEG video data.

16. The integrated circuit of claim 15 wherein the digital video decoder is an MPEG video decoder for decoding the MPEG video data.

17. The integrated circuit of claim 16 wherein the MPEG video decoder comprises one or more decode engines for concurrently decoding macroblock level video of two or more SLICEs.

18. The integrated circuit of claim 17 wherein the one or more decode engines include two decode engines, wherein each decode engine concurrently decodes macroblock level video of two SLICEs.

22. The integrated circuit of claim 1 wherein the analog video data is in a format selected from a group consisting of PAL, NTSC, Y/C (S-video), SECAM, RGB, YPBPR, YCBCR and YUV formats.

23. The integrated circuit of claim 1 wherein the display engine converts the format of the data representing graphics to a common format.

24. The integrated circuit of claim 23 wherein the common format includes a YUV-alpha format.

27. The integrated circuit of claim 1 wherein the display engine includes a single-port SRAM configured equivalently as a dual-port SRAM.

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31. A method of processing video and graphics in an integrated circuit comprising the steps of:

receiving an analog video;

receiving data representing graphics;

receiving a plurality of compressed data streams, the compressed data streams including video data;

decoding the analog video to generate digitized analog video;

blending the data representing graphics to generate blended graphics;

processing the video data to generate decoded video data; and

blending the digitized analog video, the blended graphics and the decoded video data to provide an output of blended video and graphics.

32. The method of processing video and graphics in an integrated circuit of claim 31 wherein the step of receiving a plurality of compressed data streams comprises the step of receiving one or more MPEG Transport streams.

34. The method of processing video and graphics in an integrated circuit of claim 31 wherein the video data include HDTV video data.

35. The method of processing video and graphics in an integrated circuit of claim 31 wherein the video data include SDTV video data.

36. The method of processing video and graphics in an integrated circuit of claim 31 further comprising the step of coupling a CPU to one or more peripheral devices.

37. The method of processing video and graphics in an integrated circuit of claim 36 wherein the step of coupling a CPU comprises the step of coupling the CPU to one or more PCI devices.

38. The method of processing video and graphics in an integrated circuit of claim 36 wherein the step of coupling a CPU comprises the step of coupling the CPU to one or more memory devices.

39. The method of processing video and graphics in an integrated circuit of claim 36 wherein the step of coupling a CPU comprises the step of coupling the CPU to one or more devices internal to the integrated circuit.

40. The method of processing video and graphics in an integrated circuit of claim 31 wherein the plurality of compressed data streams include audio data, and the method further comprises the step of decoding the audio data.

41. The method of processing video and graphics in an integrated circuit of claim 31 wherein at least one of the plurality of compressed data streams include data other than the video data or audio data.

42. The method of processing video and graphics in an integrated circuit of claim 31 further comprising the step of reading the value of a packet identification field of each data packet from the plurality of compressed data streams and accepting or rejecting data packets based on the value.

44. The method of processing video and graphics in an integrated circuit of claim 31 wherein the plurality of compressed data streams include encrypted data, and the method further comprises the step of decrypting the encrypted data.

45. The method of blending video and graphics in an integrated circuit of claim 31, wherein the video data include MPEG video data included in at least one MPEG Transport stream, and wherein the method further comprises the step of extracting the MPEG video data.

46. The method of blending video and graphics in an integrated circuit of claim 45 wherein the step of processing the video data comprises the step of decoding the MPEG video data.

47. The method of blending video and graphics in an integrated circuit of claim 46 wherein the step of decoding the MPEG video data comprises the step of concurrently decoding macroblock level video of two or more SLICES.

48. The method of blending video and graphics in an integrated circuit of claim 46 wherein the step of decoding the MPEG video data comprises the step of concurrently decoding macroblock level video of four or more SLICES.

51. The method of blending video and graphics in an integrated circuit of claim 45 wherein the step of processing the video data comprises the step of accessing the MPEG video data in one of pre-defined orders that are efficient for MPEG decoding.

52. The method of blending video and graphics in an integrated circuit of claim 31 wherein the analog video is in a format selected from a group consisting of PAL, NTSC, Y/C (S-video), SECAM, RGB, YP_BP_R, YC_BC_R and YUV formats.

53. The method of blending video and graphics in an integrated circuit of claim 31 wherein the step of blending the data representing graphics comprises the step of converting the format of the data representing graphics to a common format.

54. The method of blending video and graphics in an integrated circuit of claim 53 wherein the common format includes a YUV-alpha format.

57. The method of blending video and graphics in an integrated circuit of claim 31 further comprising the step of configuring a single-port SRAM equivalently as a dual-port SRAM.

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61. An integrated circuit comprising:

means for receiving analog video;

means for receiving data representing graphics having different formats;

means for receiving a plurality of compressed data streams, the compressed data streams including MPEG video data;

means for decoding the analog video to generate digitized analog video;

means for converting the formats of the data representing graphics to have a common format suitable for blending;

means for blending the data representing graphics having the common format to generate blended graphics;

means for processing the video data to generate decoded video data; and

means for blending the digitized analog video, the blended graphics and the decoded video data to provide an output of blended video and graphics.