Method and circuit for multiplying signals with a transistor having more than one independent gate structure

• US 20050124120A1
• Filed: 12/05/2003
• Published: 06/09/2005
• Est. Priority Date: 12/05/2003
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Mathew, Leo, Du, Yang
• Granted Patent: US 6,969,656 B2
• Time in Patent Office: Days
• US Class Current: 438/283
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A double gate semiconductor device (2006) is used beneficially as a multiplier (2000). The double gate semiconductor device (2006) has a lateral fin (105) as the channel region with the gates formed opposite each other on both sides of the fin. The lateral positioning of the fin provides symmetry between the two gates. To increase drive current, multiple transistors are easily connected in parallel by having a continuous fin structure (2106) with alternating source/drain terminals (2120, 2122, 2124, 2126) in which the sources are connected together and the drains are connected together. Gates (2116, 2110) are positioned between each pair of adjacent source/drain terminals and electrically connected together. The multiplier (2000) may also be used as a mixer and further as a phase detector.

Claims

1. A method for multiplying a first signal and a second signal, comprising:

providing a substrate and a semiconductor structure over the substrate, the seniiconductor structure having a first sidewall, a second sidewall, and a top surface;

depositing at least one substantially conformal layer over the substrate, wherein the at least one substantially conformal layer comprises at least a layer of gate material, wherein the at least one substantially conformal layer has a top surface at a height over the semiconductor structure;

forming a substantially planar layer over the substrate below the height of the top surface of the at least one substantially conformal layer over the semiconductor structure;

non-abrasively etching through the layer of gate material over the lop surface of the semiconductor structure;

patterning the at least one substantially conformal layer to form a gate structure prior to the forming the substantially planar layer over the substrate, wherein the non-abrasive etching through the layer of gate material over the top surface of the semiconductor structure further includes etching through the layer of gate material of the gate structure over the top surface of the semiconductor structure to form a first gate portion and a second gate portion that are electrically isolated;

forming symmetrical source and drain regions relative to the first and second gate portions such that a channel region will be formed under the first and second gates during operation of the semiconductor structure, wherein there exists plane parallel to the substrate, and wherein a portion of each of the source region, the drain region and the channel region are within the plane;

applying the first signal to the first gate portion, wherein the first signal is time-varying; and

applying the second signal to the second gate portion, wherein the second signal is time-varying.

2. The method of claim 1, wherein the first gate portion has a portion running generally parallel to a surface of the substrate, the method further comprising forming a contact on the portion of the layer of gate material running generally parallel to the surface of the substrate for receiving the first mixer signal.

3. The method of claim 1, wherein forming the substantially planar layer comprises:

depositing material of the substantially planar layer to a height above the height of the top surface of the at least one substantially conformal layer; and

etching back the material of the substantially planar layer to a height below the height of the top surface of the at least one substantially conformal layer to expose the top surface of the at least one substantially conformal layer over the top surface of the semiconductor structure.

4. The method of claim 1, wherein the forming the substantially planar layer comprises depositing material of the substantially planar layer over a surface of the semiconductor substrate to a height below the height of the top surface of the at least one substantially conformal layer.

5. The method of claim 1, wherein forming the substantially planar layer comprises spinning on material of the substantially planar layer.

6. The method of claim 1, wherein the at least one substantially conformal layer further comprises a nitride layer over the layer of gate material.

7. The method of claim 6 further comprising:

etching through the nitride layer over the top surface of the semiconductor structure prior the non-abrasive etching through the layer of gate material.

8. The method of claim 1 further comprising forming a dielectric layer on the semiconductor structure prior to forming the at least one substantially conformal layer.

9. The method of claim 1, wherein the first signal is an oscillator signal and the second signal is an analog signal.

10. The method of claim 1, wherein the first signal is an oscillator signal and the second signal is a digital signal.

11. The method of claim 1, wherein the substantially planar layer includes photo resist.

12. The method of claim 1, wherein the layer of gate material is selected from one of metal and polysilicori.

13. The method of claim 1, wherein the providing the substrate further comprises providing the semiconductor structure with a plurality of sources and drains, wherein the sources are connected together and the drains are connected together.

14. The method of claim 1, wherein the at least one conformal layer includes a second substantially conformal layer formed after the layer of gate material, the second substantially conformal material is for use as an etch stop layer.

15. The method of claim 1 further comprising:

providing a dielectric structure over the top surface of the semiconductor structure, the dielectric structure having a top surface, wherein the at least one substantially conformal layer is deposited over the dielectric structure, wherein the non-abrasive etching through the layer of gate material further includes etching through the layer of gate material over the top surface of the dielectric structure.

16. The method of claim 1, further comprising:

implanting dopants at a first angle relative to the substrate of a first type into the layer of gate material in an area adjacent to the first sidewall; and

implanting dopants at a second angle relative to the substrate of a second type into the layer of gate material in an area adjacent to the second sidewall.

17. A method of multiplying a first signal and a second signal, comprising:

providing a substrate having a semiconductor structure over the substrate, the semiconductor structure having a first sidewall, a second sidewall, and a top surface;

forming a first dielectric layer on the semiconductor structure;

depositing a first substantially conformal layer of gate material over the substrate after forming the first dielectric layer;

forming a second substantially conformal layer of a material different from the first substantially conformal layer over the first substantially conformal layer;

depositing a substantially planar layer over the substrate after depositing the second substantially conformal layer;

etching through the first substantially conformal layer and the second substantially conformal layer over the top surface of the semiconductor structure to result in a first portion of the first substantially conformal layer on the first sidewall of the semiconductor structure and extending over a first portion of the substrate and a second portion of the first substantially conformal layer on the second sidewall of the semiconductor structure and extending over a second portion of the substrate, wherein the first and second portions are electrically isolated from each other;

forming symmetrical source and drain regions relative to the first and second portions such that a channel region will be formed under the first and second gates during operation of the semiconductor structure, wherein there exists a plane parallel to the substrate, and wherein a portion of each of the source region, the drain region and the channel region are within the plane;

applying the first signal to the first portion; and

applying the second signal to the second portion.

18. The method of claim 17, further comprising:

forming a first contact to the first portion of the first substantially conformal layer over the first portion of the substrate; and

,

forming a second contact to the second portion of the first substantially conformal layer over the second portion of the substrate.

19. The method of claim 18, further comprising removing the second substantially conformal layer after the etching through the first substantially conformal layer and the etching through the second substantially conformal layer.

20. The method of claim 19, wherein the substantially planar layer is a spin-on material.

21. The method of claim 17, wherein the providing the substrate further comprises providing the semiconductor structure with a plurality of sources and drains, wherein the sources are connected together and the drains are connected together.

22. The method of claim 17, wherein the forming the substantially planar layer comprises depositing material of the substantially planar layer to a height lower than a height of a top surface of the second substantially conformal layer over the top surface of the semiconductor structure.

23. The method of claim 17, further comprising etching back the substantially planar layer to lower the substantially planar layer below a height of a top surface of the second substantially conformal layer over the semiconductor structure prior to etching through the first substantially conformal layer.

24. The method of claim 17, wherein the first signal is an oscillator signal and the second signal is analog.

25. The method of claim 17, wherein the first signal is an oscillator signal and the second signal is digital.

26. A method of forming a semiconductor structure, comprising:

providing a substrate;

forming a semiconductor fin on the substrate, the fin having first and second sidewalls;

forming a layer of gate material over the substrate and the fin, the gate material including a first portion adjacent to the first sidewall of the fin and a second portion adjacent the second sidewall of the fin;

removing the layer of gate material over the semiconductor fin to leave a first gate along the first sidewall and a second gate along the second sidewall, wherein the first and second gates are electrically isolated;

forming symmetrical source and drain regions relative to the first and second gates such that a channel region will be formed under the first and second gates during operation of the semiconductor structure, wherein there exists a plane parallel to the substrate, and wherein a portion of each of the source region, the drain region and the channel region are within the plane;

applying a first signal to the first gate; and

applying a second signal to the second gate.

27. The method of claim 26, wherein the semiconductor fin has a plurality of fin portions separated by adjacent pairs of source contacts and drain contacts, wherein the source contacts are electrically connected together and the drain contacts are electrically connected together.

28. The method of claim 27, wherein the first gate comprises a first plurality of gate portions electrically connected together, wherein each of the gate portions of the first plurality of gate portions is adjacent to the first sidewall and between one of the adjacent pairs of source and drain contacts.

29. The method of claim 26, wherein the first signal is an oscillator signal and the second signal is an analog signal.

30. The method of claim 26, wherein the first signal is an oscillator signal and the second signal is a digital signal.

31-41. -41. (canceled)