Method of forming an inductor with continuous metal deposition

• US 20050124131A1
• Filed: 01/13/2005
• Published: 06/09/2005
• Est. Priority Date: 05/01/2003
• Status: Abandoned Application

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Hweing, Chit, Chu, Sanford, Chan, Lap, Verma, Purakh, Pradeep, Yelehanka Ramachandramurthy
• Application Number:
  US11/034,932
• Publication Number:
  US 20050124131A1
• Time in Patent Office: Days
• US Class Current: 438/381
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.

Claims

1-17. -17. (canceled)

18. An inductor device comprising,

a stack of dielectric layers on a semiconductor substrate, having active and passive components;

metal inductor embedded in said stack of dielectric layers; and

metal inductor encased in barrier material.

19. An inductor device according to claim 18, wherein said dielectric stack consists of one or more layers of dielectric films.

20. An inductor device according to claim 18, wherein said dielectric layer comprise inorganic, organic, and/or hybrid materials.

21. An inductor device according to claim 20, wherein said inorganic dielectric layer comprises silicon dioxide, nitridized silicon dioxide, silicon nitride, oxygen-doped silicon nitride, and/or silicon oxy-fluoride.

22. An inductor device according to claim 20, wherein said organic dielectric layer comprises poly-tetrafluoro ethylene, polyimide, poly arylenes, cyclotenes, and teflons, and/or polyimide nanofoams.

23. An inductor device according to claim 20, wherein said hybrid dielectric layer comprises spin-on glass, nanoporous silica, organo-silicate glass, methyl silsesquioxane, hydrogen silsesquioxane, and/or silica aerogels.

24. An inductor device according to claim 20, wherein said inductor-metal comprises aluminum, copper, aluminum-copper alloy, gold, and/or silver.

25. An inductor device according to claim 20, wherein said barrier material comprises Ta, TaN, and/or TiN.