Data element size control within parallel lanes of processing

• US 20050125631A1
• Filed: 07/13/2004
• Published: 06/09/2005
• Est. Priority Date: 12/09/2003
• Status: Abandoned Application

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Seal, David James, Symes, Dominic Hugo, Kershaw, Daniel, Ford, Simon Andrew
• Application Number:
  US10/889,471
• Publication Number:
  US 20050125631A1
• Time in Patent Office: Days
• US Class Current: 712/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants

Abstract

Within a SIMD processor 2 data processing instructions are provided which specify parallel lanes of processing to be performed upon respective data elements. The data elements are permitted to vary in size whilst the number of processing lanes remain constant. Thus, the destination register size for a multiplication may be double the source register size.

Claims

1. Apparatus for processing data, said apparatus comprising:

processing logic responsive to a data processing instruction to perform a data processing operation in a plurality of parallel lanes of processing upon respective source data elements accessed from one or more source registers so as to generate respective destination data elements within one or more destination registers;

wherein

said processing logic is operable to maintain said number of lanes of processing constant whilst data element size within said lanes of processing differs between at least one of said one or more source registers and at least one of said one or more destination registers.

2. Apparatus as claimed in claim 1, wherein said data element size within said one or more destination registers is twice said data element size within at least one of said one or more source registers.

3. Apparatus as claimed in claim 1, wherein said data element size within said one or more destination registers is half said data element size within at least one of said one or more source registers.

4. Apparatus as claimed in claim 2, wherein said data processing operation is multiplying together respective source data elements from each lane of processing within two source registers to generate respective destination data elements within a destination register.

5. Apparatus as claimed in claim 2, wherein said data processing operation is adding together respective source data elements from each lane of processing within two source registers to generate respective destination data elements within a destination register.

6. Apparatus as claimed in claim 2, wherein said data processing operation is subtracting from one another respective source data elements from each lane of processing within two source registers to generate respective destination data elements within a destination register.

7. Apparatus as claimed in claim 2, wherein said data processing operation is shifting respective source data elements from each lane of processing within a source register to generate respective destination data elements within a destination register.

8. Apparatus as claimed in claim 1, wherein said data processing instruction specifies for said data processing operation data element sizes and register sizes for said one or more source registers and said one or more destination registers.

9. Apparatus as claimed in claim 8, further comprising register accessing logic operable to map said one or more source registers and said one or more destination registers to portions of a register data store dependent upon said register sizes for said one or more source registers and said one or more destination registers such that a data element stored within a portion of said register data store is accessible as a part of respective different registers of differing register size.

10. Apparatus as claimed in claim 1, wherein said destination data elements within said one or more destination registers serve a source data elements within one or more source registers corresponding to one or more subsequent data processing instruction whilst maintaining constant said number of lanes of processing.

11. A method of processing data, said method comprising the steps of:

in response to a data processing instruction performing a data processing operation in a plurality of parallel lanes of processing upon respective source data elements accessed from one or more source registers so as to generate respective destination data elements within one or more destination registers;

wherein

said number of lanes of processing is maintained constant whilst data element size within said lanes of processing differs between at least one of said one or more source registers and at least one of said one or more destination registers.

12. A method as claimed in claim 11, wherein said data element size within said one or more destination registers is twice said data element size within at least one of said one or more source registers.

13. A method as claimed in claim 11, wherein said data element size within said one or more destination registers is half said data element size within at least one of said one or more source registers.

14. A method as claimed in claim 12, wherein said data processing operation is multiplying together respective source data elements from each lane of processing within two source registers to generate respective destination data elements within a destination register.

15. A method as claimed in claim 12, wherein said data processing operation is adding together respective source data elements from each lane of processing within two source registers to generate respective destination data elements within a destination register.

16. A method as claimed in claim 12, wherein said data processing operation is subtracting from one another respective source data elements from each lane of processing within two source registers to generate respective destination data elements within a destination register.

17. A method as claimed in claim 12, wherein said data processing operation is shifting respective source data elements from each lane of processing within a source register to generate respective destination data elements within a destination register.

18. A method as claimed in claim 11, wherein said data processing instruction specifies for said data processing operation data element sizes and register sizes for said one or more source registers and said one or more destination registers.

19. A method as claimed in claim 18, further comprising register accessing logic operable to map said one or more source registers and said one or more destination registers to portions of a register data store dependent upon said register sizes for said one or more source registers and said one or more destination registers such that a data element stored within a portion of said register data store is accessible as a part of respective different registers of differing register size.

20. A method as claimed in claim 11, wherein said destination data elements within said one or more destination registers serve a source data elements within one or more source registers corresponding to one or more subsequent data processing instruction whilst maintaining constant said number of lanes of processing.

21. A computer program product comprising a computer program including at least one data processing instruction operable to control processing logic to perform a method as claimed in claim 11.