Digital reliability monitor having autonomic repair and notification capability

• US 20050125707A1
• Filed: 12/04/2003
• Published: 06/09/2005
• Est. Priority Date: 12/04/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Bonaccio, Anthony R., Ventrone, Sebastian T., Tonti, William R., LeStrange, Michael
• Granted Patent: US 7,287,177 B2
• Time in Patent Office: Days
• US Class Current: 713/502
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom

Abstract

An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when the cycle counter reaches a pre-determined cycle count.

Claims

1. An integrated circuit, comprising:

a pulse generator adapted to generate a pulsed signal;

a cycle counter adapted to count cycles of said pulsed signal;

one or more repairable circuit elements; and

a repair processor adapted to repair a repairable circuit element when said cycle counter reaches a pre-determined cycle count.

2. The integrated circuit of claim 1, wherein said repair processor, replaces said repairable circuit element with a redundant circuit element having the same function as said repairable circuit element.

3. The integrated circuit if claim 1, wherein said pulsed signal is a clock signal and said repairable circuit element is responsive to said clock signal.

4. The integrated circuit of claim 1, further including a memory circuit adapted to store a cycle count of the number of cycles counted since an initial power up and to resume counting from said stored cycle count after a power down/power up cycle of said integrated circuit.

5. The integrated circuit of claim 1, wherein:

said cycle counter is adapted to generate a trigger signal when said predetermined cycle count is reached; and

said repair processor is adapted to receive said trigger signal and affect a repair of said repairable circuit element when said trigger signal is received.

6. The integrated circuit of claim 5, wherein said trigger signal comprises a subset of a set of bits encoding a current cycle count of said cycle counter.

7. The integrated circuit of claim 1, wherein said repairable circuit element is selected from the group consisting of a digital circuit, an analog circuit, a memory circuit, a latch, a logic gate, a group of logic gates, an individual devices, a transistor, a diode, a resistors, capacitor, an inductor and a wire.

8. The integrated circuit of claim 1, wherein said repairable circuit element is implemented in a field programmable gate array and said repair processor programs a replacement of selected gates of said field programmable gate array with previously unused gates of said field programmable gate array.

9. The integrated circuit of claim 1, further including a fuse bank for storing information used to implement a repair of said repairable circuit element.

10. The integrated circuit of claim 1, wherein in said repair processor is adapted to perform multiple repairs by repairing previously repaired repairable circuit elements.

11. The integrated circuit of claim 1, further including:

a redundant cycle counter; and

wherein said repair processor is adapted to replace said cycle counter with said redundant cycle counter when said cycle counter reaches a fixed cycle count.

12. A method of preemptively repairing an integrated circuit, comprising:

(a) a pulse generated adapted to generate a pulsed signal;

(b) providing a cycle counter adapted to count cycles of said pulsed signal;

(c) providing one or more repairable circuit elements; and

(d) providing a repair processor adapted to repair a repairable circuit element when said cycle counter reaches a pre-determined cycle count.

13. The method of claim 12, wherein said step (d) includes replacing said one or more repairable circuit element with a redundant circuit element having the same function as said repairable circuit element.

14. The method if claim 12, wherein said pulsed signal is a clock signal and said repairable circuit element is responsive to said clock signal.

15. The method of claim 12, further including a memory circuit adapted to store a cycle count of a number of cycles counted since an initial power up and to resume counting from said stored cycle count after a power down/power up cycle of said integrated circuit.

16. The method of claim 12, wherein:

said cycle counter is adapted to generate a trigger signal when said predetermined cycle count is reached; and

said repair processor is adapted to receive said trigger signal and affect a repair of said repairable circuit element when said trigger signal is received.

17. The method of claim 16, wherein said trigger signal comprises a subset of a set of bits encoding a current cycle count of said cycle counter.

18. The method of claim 12, wherein said repairable circuit element is selected from the group consisting of a digital circuit, an analog circuit, a memory circuit, a latch, a logic gate, a group of logic gates, an individual device, a transistor, a diode, a resistor, a capacitor, an inductor and a wire.

19. The method of claim 12, wherein said repairable circuit element is implemented in a field programmable gate array and said repair processor programs a replacement of selected gates of said field programmable gate array with previously unused gates of said field programmable gate array.

20. The method of claim 12, further including providing a fuse bank for storing information used to implement a repair of said repairable circuit element.

21. The method of claim 12, wherein in said repair processor is adapted to perform multiple repairs by repairing previously repaired repairable circuit elements.

22. The method of claim 12, further including:

providing a redundant cycle counter; and

said repair processor automatically replacing said cycle counter with said redundant cycle counter when said cycle counter reaches a fixed cycle count.

23. A method for designing a repairable integrated circuit, comprising:

generating an integrated circuit design from a design library of circuit elements;

simulating said integrated circuit design and generating a switching report for circuit elements of said integrated circuit design;

selecting a circuit element responsive to a pulsed signal of said integrated circuit design based on said switching report;

selecting a repairable circuit element from said design library, said repairable circuit element having the same function as said selected circuit element and allowing multiple connection paths; and

inserting said selected repairable circuit element, a cycle counter adapted to count cycles of said pulsed signal and repair processor adapted to repair said repairable circuit element when said cycle counter reaches a pre-determined value into said integrated circuit design.

24. The method of claim 23, wherein said switching report indicates a number of state toggles of each selected circuit element performed during said simulation.

25. The method of claim 23, wherein said repairable circuit element is selected from the group consisting of a digital circuit, an analog circuit, a memory circuit, a latch, a logic gate, a group of logic gates, an individual device, a transistors, a diode, a resistor, a capacitor, an inductors and a wire.

26. The method of claim 23, wherein said repairable circuit element is implemented in a field programmable gate array having spare gates and said repair processor includes a circuit for programming said field programmable array to use programmed spare gates in place of the gates originally programmed to implement said repairable circuit element.

27. A computer system comprising a processor, an address/data bus coupled to said processor, and a computer-readable memory unit adapted to be coupled to said processor, said memory unit containing instructions that when executed by said processor implement a method for a method for designing a repairable integrated circuit, said method comprising the computer implemented steps of:

generating an integrated circuit design from a design library of circuit elements;

simulating said integrated circuit design and generating a switching report for circuit elements of said integrated circuit design;

selecting a circuit element responsive to a pulsed signal of said integrated circuit design based on said switching report;

selecting a repairable circuit element from said design library, said repairable circuit element having the same function as said selected circuit element and allowing multiple connection paths; and

inserting said selected repairable circuit element, a cycle counter adapted to count cycles of said pulsed signal and repair processor adapted to repair said repairable circuit element when said cycle counter reaches a pre-determined value into said integrated circuit design.

28. The system of claim 27, wherein said switching report indicates a number of state toggles of said circuit element performed during said simulation.

29. The system of claim 27, wherein said repairable circuit element is selected from the group consisting of a digital circuit, an analog circuit, a memory circuit, a latch, a logic gate, a group of logic gates, an individual device, a transistor, a diode, a resistor, a capacitor, an inductor and a wire.

30. The method of claim 27, wherein said repairable circuit element is implemented in a field programmable gate array having spare gates and said repair processor includes a circuit for programming said field programmable array to use programmed spare gates in place of the gates originally programmed to implement said repairable circuit element.