Communications system for implementation of synchronous, multichannel, galvanically isolated instrumentation devices

• US 20050125709A1
• Filed: 05/28/2004
• Published: 06/09/2005
• Est. Priority Date: 12/05/2003
• Status: Active Grant

• Current Assignee: Keysight Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Vulovic, Marko, Chan, Buck H., McKim, James B. Jr., Carlson, Richard A., Hyde, John W., Kenny, John F.
• Granted Patent: US 7,302,282 B2
• Time in Patent Office: Days
• US Class Current: 714/25
• CPC Class Codes: G06F 11/273 Tester hardware, i.e. output processing circuits G06F11/263 takes precedence

Abstract

An apparatus and method for synchronous communications using a serial data stream employs a housing with a controller and a back plane. The housing accepts one or more modules for interconnection with the back plane. The back plane distributes power to the modules and provides a communication link from the controller to each module. Each communication link includes a data out line, a data in line and a clock line, where each clock line is derived from one clock source.

Claims

1. An apparatus comprising:

a housing having a controller and a back plane,

said housing accepting at least first and second modules for interconnection with said back plane, said back plane distributing power to each module, said backplane also providing a dedicated serial communication link from said controller to respective ones of said modules, each communication link having a data out line, a data in line and a clock line, each clock line being derived from one clock source, wherein all connections between said at least first and second modules interconnect with said back plane through galvanic isolators and wherein said controller transmits send packets over said data out lines and wherein a start of frame signal for each said send packet occurs on a single edge of said clock source.

2. An apparatus as recited in claim 1 wherein said communications link comprises a JTAG communications link.

3. An apparatus as recited in claim 1 wherein said communications link comprises no more than said data out line, said data in line and said clock line.

4. An apparatus as recited in claim 1 wherein said galvanic isolators are disposed on each said at least first and second modules.

5. An apparatus as recited in claim 1 wherein said first module comprises a power supply.

6. An apparatus as recited in claim 5 wherein said first module further comprises first waveform generator and first digitizer for control and measurement of an output voltage and second waveform generator and second digitizer for control and measurement of an output current.

7. An apparatus as recited in claim 1 wherein said first module comprises an electronic load.

8. An apparatus as recited in claim 7 wherein said electronic load further comprises a waveform generator for control of an input current and first and second digitizers for control and measurement of an input voltage.

9. An apparatus as recited in claim 7 wherein said electronic load further comprises a waveform generator for control of an input voltage and first and second digitizers for control and measurement of an input current.

10. An apparatus as recited in claim 7 wherein said electronic load further comprises a waveform generator for control of an input voltage and first and second digitizers for control and measurement of an input current adapted to maintain a constant resistance load.

11. An apparatus as recited in claim 3 wherein said controller transmits a send data packet on each said data out line synchronized to said clock source, and said at least first and second modules each transmits a receive packet on said data in line synchronized to said clock source wherein said receive packet is delayed from said send packet.

12. An apparatus as recited in claim 11 wherein said send packet is delayed from said receive packet by an integer number of clock cycles.

13. An apparatus as recited in claim 11 wherein said send packet is delayed from said receive packet by two cycles of said clock.

14. An apparatus as recited in claim 11 wherein a first send packet and a first receive packet are sent in a single communications frame, and wherein said first receive packet comprises a status bit and said first send packet comprises a responsive bit to said status bit, wherein said status bit is sent prior to said responsive bit, wherein said responsive bit is sent to selected receiving modules, and wherein said receiving modules initiate an action upon receipt of said responsive bit.

15. An apparatus as recited in claim 14 wherein said status bit comprises a fast protect bit indicating a condition in at least said first module that warrants a response by said second module.

16. An apparatus as recited in claim 14 wherein said response comprises an output inhibit.

17. An apparatus as recited in claim 13 wherein a first bit for each said receive packet occurs on a single edge of said clock source.

18. An apparatus as recited in claim 1 wherein said controller transmits a send data packet on each said data out line synchronized to said clock source, said send data packet containing at least one trigger bit.

19. An apparatus as recited in claim 18 wherein said at least one trigger bit is received by said first module and initiates an operation in said first module.

20. An apparatus as recited in claim 1 wherein said controller transmits a send data packet on each said data out line synchronized to said clock source, each said send data packet containing a respective trigger signal at a same bit location in each said send packet.

21. An apparatus as recited in claim 20 wherein said respective trigger signals are received by said at least first and second modules synchronized with a single edge of said clock source and initiate an operation in each said module at a substantially similar time.

22. An apparatus as recited in claim 18 wherein said send packet comprises more than one trigger bit and each trigger bit initiates a separate action in said module.

23. An apparatus as recited in claim 18 wherein said send packet comprises more than one trigger bit and each trigger bit initiates a same action in said module.

24. An apparatus as recited in claim 1 wherein said controller transmits each said send data packet during a single fixed length communications frame at regular time intervals.

25. An apparatus as recited in claim 24 wherein each said module transmits a receive data packet on each said data in line during said frame synchronized to said clock source and to said start of frame signal.

26. An apparatus as recited in claim 1 wherein said controller communicates with said first module at a first rate of communication and with said second module at a second rate of communication wherein said first rate is different from said second rate, said first rate and said second rates synchronized with said clock source.

27. An apparatus as recited in claim 1 wherein a controller on said module includes JTAG functionality and said controller detects a presence of said module and said module provides an identification code to said controller over said communications link using said JTAG functionality and said controller thereafter configures each said identified module by transmitting a serial data stream using said JTAG functionality.

28. An apparatus as recited in claim 3 wherein each said module has a module processor having JTAG functionality and said data out, data in, and clock lines are connected to a communications port of said module processor and TDI, TDO, and TCK inputs, respectively, of a JTAG port of said module processor through respective isolation elements.

29. An apparatus as recited in claim 28 and further comprising a circuit that generates a TDI window and a TMS window on one of the serial communications link lines to maintain and control test mode select states in a module processor and to transmit JTAG test control (TMS) information while simultaneously using said same serial communications lines to transmit JTAG test input (TDI) data.

30. An apparatus as recited in claim 28 wherein a memory element de-multiplexes and maintains a TMS data stream to TMS of the JTAG port upon and following initial communication with said module over said communications link after a module reset.

31. An apparatus as recited in claim 30 wherein said controller configures said module processor over said communications link using standard JTAG protocols.

32. An apparatus as recited in claim 31 wherein said module processor presets said memory element upon completion of said module processor configuration thereby causing a JTAG “

test logic reset”

state which terminates JTAG operation while enabling initiation of a different mode of serial communication via the same said data in, data out, and clock lines.

33. An apparatus as recited in claim 1 wherein said controller selectively resets one or more of said modules by selectively forcing respective ones of said clock lines to a consistent state for a predefined amount of time.

34. An apparatus as recited in claim 33 wherein said controller detects, identifies and configures said one or more reset modules.

35. A method for configuring a module over a communications link, said module comprising a module processor having JTAG functionality, said communications link having three serial communications lines defined as data out, data in, and clock lines connected to a serial communications port on said module processor, said three serial communications lines also connected to TDI, TDO, and TCK pins, respectively, of a JTAG port of said module processor, the method comprising the steps of:

placing said module processor in a JTAG test mode by latching into a memory element a bit value on said data out line using said clock line, an output of said memory element connected to TMS of said JTAG port,

configuring said module processor through said JTAG port using said serial communications lines,

taking said module processor out of said JTAG test mode by presetting said memory element upon completion of said step of configuring, and

initiating serial communications over said communications link with said module.

36. A method as recited in claim 35 wherein said communications link comprises a JTAG communications link.

37. A method as recited in claim 35 wherein said communications link comprises no more than said three lines.

38. A method as recited in claim 35 wherein said module comprises a power supply.

39. A method as recited in claim 38 wherein said first module further comprises first waveform generator and first digitizer for control and measurement of an output voltage and second waveform generator and second digitizer for control and measurement of an output current.

40. A method as recited in claim 35 wherein said first module comprises an electronic load.

41. A method as recited in claim 40 wherein said electronic load further comprises a waveform generator for control of an input current and first and second digitizers for control and measurement of an input voltage.

42. A method as recited in claim 40 wherein said electronic load further comprises a waveform generator for control of an input voltage and first and second digitizers for control and measurement of an input current.

43. A method as recited in claim 40 wherein said electronic load further comprises a waveform generator for control of an input voltage and first and second digitizers for control and measurement of an input current adapted to maintain a constant resistance load.

44. A method as recited in claim 35 and further comprising the step of said module identifying itself over said serial communications link prior to said step of configuring.

45. A method as recited in claim 44 wherein said step of identifying comprises the step of reading a serial bit stream over said communications link that uniquely identifies a type of module, thereby defining said step of configuring said module.

46. A method as recited in claim 35 wherein there is more than one module installed in a housing, said method further comprising the step of repeating said steps of placing, configuring, taking and initiating for each module.

47. A method as recited in claim 46 wherein a first module comprises a waveform generator and a second module comprises a digitizer.

48. A method as recited in claim 35 wherein there is more than one module installed in a housing, wherein said step of initiating serial communications over said communications link further comprises communicating with a first module at a first rate of communications and communicating with a second module at a second rate of communication wherein said first rate is different from said second rate, said first rate and said second rates synchronized with a common clock source.

49. A method for synchronous triggering of events in multiple modules, each module receiving a serial bit stream over a respective communications link, each said communications link comprising a data out and a clock line, each said clock line derived from a single clock source, the method comprising the steps of:

transmitting a send packet over said data out line to each module synchronous with said clock source wherein said send packet contains at least one bit position defined as a trigger bit and

triggering events in respective ones of said modules upon receipt of respective ones of said trigger bits.

50. A method as recited in claim 49 wherein said step of triggering an event comprises waveform digitization.

51. A method as recited in claim 49 wherein said step of triggering an event comprises waveform synthesis.

52. A method as recited in claim 49, said communications link further comprising a data in line and further comprising the steps of receiving a serial bit stream over said data in line comprising a receive packet from each said module, wherein a predefined bit in each said receive packet comprises an indication that a measurement is triggered.

53. A method as recited in claim 52 wherein said receive packet from each module further comprises a plurality of bits reflecting synchronous results of said triggered measurement.

54. An apparatus for performing synchronous triggering of events in multiple modules comprising

a housing comprising a controller and receiving two or more modules,

a respective serial communications link between said controller and each of said two or more modules, each said communications link comprising a data out and a clock line, each said clock line derived from a single clock source,

means for transmitting a send packet over said data out line to each module synchronous with said clock source wherein said send packet contains at least one bit position defined as a trigger bit, and

means in each said module for triggering a module specific event upon receipt of respective ones of said trigger bits.

55. An apparatus as recited in claim 54 wherein said event comprises waveform digitization.

An apparatus as recited in claim 54 wherein said event comprises waveform synthesis.

56. An apparatus as recited in claim 54 wherein said event comprises waveform digitization and waveform synthesis on separate channels of said module.

57. An apparatus as recited in claim 54, said communications link further comprising a data in line and further comprising means for receiving a serial bit stream over said data in line comprising a receive packet from each said module, wherein a predefined bit in each said receive packet comprises an indication that a measurement is triggered.

58. An apparatus as recited in claim 57 wherein said receive packet from each module further comprises a plurality of bits reflecting synchronous results of said triggered measurement.

59. An apparatus comprising:

a housing having a controller, a module and a backplane, said backplane distributing power to the module, said backplane also providing a dedicated serial communication link from said controller to said module, said communication link defined as a data out line, a data in line and a clock line, said clock line being derived from a clock source, wherein all connections between said module and said controller through said backplane interconnect through galvanic isolators and wherein said controller transmits send packets over said data out lines and wherein a start of frame signal for each said send packet occurs on a single edge of said clock source.

60. An apparatus as recited in claim 59 wherein said galvanic isolators are disposed in said module.

61. An apparatus as recited in claim 59 wherein said controller transmits said send packet on said data out line synchronized to said clock source, and said module transmits a receive packet on said data in line synchronized to said clock source wherein said receive packet is delayed from said send packet.

62. An apparatus as recited in claim 61 wherein said send packet is delayed from said receive packet by an integer number of clock cycles.

63. An apparatus as recited in claim 62 wherein said send packet is delayed from said receive packet by two cycles of said clock.

64. An apparatus as recited in claim 61 wherein a first bit for each said receive packet occurs on a single edge of said clock source.

65. An apparatus as recited in claim 59 wherein said controller transmits said send data packet on said data out line synchronized to said clock source and said send data packet contains at least one trigger bit.

66. An apparatus as recited in claim 65 wherein said at least one trigger bit is received by said module and initiates an operation in said module.

67. An apparatus as recited in claim 59 wherein said send packet comprises more than one trigger bit and each trigger bit initiates a separate action in said module.

68. An apparatus as recited in claim 59 wherein said send packet comprises more than one trigger bit and each trigger bit initiates a same action in said module.

69. An apparatus as recited in claim 59 wherein said controller transmits each said send data packet during a single fixed length communications frame at regular time intervals.

70. An apparatus as recited in claim 69 wherein said module transmits a receive data packet on said data in line during said frame synchronized to said clock source and to said start of frame signal.

71. An apparatus as recited in claim 59 wherein a controller on said module includes JTAG functionality and said controller detects a presence of said module and said module provides an identification code to said controller over said communications link using said JTAG functionality and said controller thereafter configures said identified module by transmitting a serial data stream using said JTAG functionality.

72. An apparatus as recited in claim 59 wherein said module has a module processor having JTAG functionality and said clock, data out, and data in lines are connected to a communications port of said module processor and TCK, TDI and TDO inputs, respectively, of a JTAG port of said module processor through respective isolation elements.

73. An apparatus as recited in claim 72 and further comprising a circuit that generates a TDI window and a TMS window on one of the serial communications link lines to maintain and control test mode select states in a module processor and to transmit JTAG test control (TMS) information while simultaneously using said serial communications link to transmit JTAG test input (TDI) data.

74. An apparatus as recited in claim 72 wherein a memory element de-multiplexes and maintains a TMS data stream to TMS of the JTAG port true upon and following initial communication with said module over said communications link after a module reset.

75. An apparatus as recited in claim 72 wherein said controller configures said module processor over said communications link using standard JTAG protocols.

76. An apparatus as recited in claim 74 wherein said module processor presets said memory element upon completion of said module processor configuration thereby causing a JTAG “

test logic reset”

state which terminates JTAG operation while enabling initiation of a different mode of serial communication via the same said data in, data out, and clock lines.

77. An apparatus as recited in claim 59 wherein said controller selectively resets one or more of said modules by selectively forcing respective ones of said clock lines to a consistent state for a predefined amount of time.

78. An apparatus as recited in claim 77 wherein said controller detects, identifies and configures said one or more reset modules.

79. A test apparatus comprising a housing and backplane and adapted to accept at least one module comprising a controller communicating with each said module over a serial communications link wherein each said module is galvanically isolated from said housing and said controller.

80. A test apparatus as recited in claim 79 wherein said communications link comprises a JTAG communications link.

81. A test apparatus as recited in claim 79 wherein said communications link comprises no more than said data out line, said data in line and said clock line.

82. A test apparatus as recited in claim 79 wherein a galvanic isolator is disposed on said module.

83. A test apparatus as recited in claim 79 and further adapted to accept two or more of said modules.

84. An apparatus as recited in claim 79 wherein said first module comprises a power supply.

85. An apparatus as recited in claim 84 wherein said first module further comprises first waveform generator and first digitizer for control and measurement of an output voltage and second waveform generator and second digitizer for control and measurement of an output current.

86. An apparatus as recited in claim 79 wherein said first module comprises an electronic load.

87. An apparatus as recited in claim 86 wherein said electronic load further comprises a waveform generator for control of an input current and first and second digitizers for control and measurement of an input voltage.

88. An apparatus as recited in claim 86 wherein said electronic load further comprises a waveform generator for control of an input voltage and first and second digitizers for control and measurement of an input current.

89. An apparatus as recited in claim 86 wherein said electronic load further comprises a waveform generator for control of an input voltage and first and second digitizers for control and measurement of an input current adapted to maintain a constant resistance load.

90. A test apparatus as recited in claim 81 wherein said controller transmits a send data packet on each said data out line synchronized to a clock source, and said module transmits a receive packet on said data in line synchronized to said clock source wherein said receive packet is delayed from said send packet.

91. A test apparatus as recited in claim 90 wherein said send packet is delayed from said receive packet by an integer number of clock cycles.

92. A test apparatus as recited in claim 90 wherein said send packet is delayed from said receive packet by two cycles of said clock source.

93. A test apparatus as recited in claim 90 wherein a first send packet and a first receive packet are sent in a single communications frame, and wherein said first receive packet comprises a status bit and said first send packet comprises a responsive bit to said status bit, wherein said status bit is sent prior to said responsive bit, wherein said responsive bit is sent to selected receiving modules, and wherein said receiving modules initiate an action upon receipt of said responsive bit.

94. A test apparatus as recited in claim 93 wherein said status bit comprises a fast protect bit indicating a condition in one of said modules that warrants a response by another one of said modules.

95. A test apparatus as recited in claim 94 wherein said response comprises an output inhibit.

96. An apparatus as recited in claim 90 wherein a first bit for each said receive packet occurs on a single edge of said clock source.

97. A test apparatus as recited in claim 79 wherein said controller initiates an event in one of said modules via said communications link.

98. A test apparatus as recited in claim 79 wherein said controller transmits a send data packet on each said data out line synchronized to a clock source, said send data packet containing at least one trigger bit.

99. A test apparatus as recited in claim 98 wherein said at least one trigger bit is received by said first module and initiates an operation in said first module.

100. A test apparatus as recited in claim 79 wherein said controller transmits a send data packet on each said data out line synchronized to a clock source, each said send data packet containing a respective trigger signal at a same bit location in each said send packet.

101. A test apparatus as recited in claim 100 wherein said respective trigger signals are received by said modules synchronized with a single edge of said clock source and initiate an operation in each said module at a substantially similar time.

102. A test apparatus as recited in claim 98 wherein said send packet comprises more than one trigger bit and each trigger bit initiates a separate action in said module.

103. A test apparatus as recited in claim 98 wherein said send packet comprises more than one trigger bit and each trigger bit initiates a same action in said module.

104. A test apparatus as recited in claim 79 wherein said controller transmits each said send data packet during a single fixed length communications frame at regular time intervals.

105. A test apparatus as recited in claim 104 wherein each said module transmits a receive data packet on each said data in line during said frame synchronized to a clock source and to said start of frame signal.

106. A test apparatus as recited in claim 83 wherein said controller communicates with a first module at a first rate of communication and with a second module at a second rate of communication wherein said first rate is different from said second rate, said first rate and said second rates synchronized with a clock source.

107. A test apparatus as recited in claim 79 wherein said module self identifies prior to module configuration.

108. A test apparatus as recited in claim 107 wherein said controller configures said module according to information in said self identification.

109. A test apparatus as recited in claim 108 wherein said controller configures said module using JTAG protocols.

110. A test apparatus as recited in claim 81 wherein said module has a module processor having JTAG functionality and said data out, data in, and clock lines are connected to a communications port of said module processor and TDI, TDO, and TCK inputs, respectively, of a JTAG port of said module processor through respective isolation elements.

111. A test apparatus as recited in claim 110 and further comprising a circuit that generates a TDI window and a TMS window on one of the serial communications link lines to maintain and control test mode select states in a module processor and to transmit JTAG test control (TMS) information while simultaneously using said same serial communications lines to transmit JTAG test input (TDI) data.

112. A test apparatus as recited in claim 110 wherein a memory element de-multiplexes and maintains a TMS data stream to TMS of the JTAG port upon and following initial communication with said module over said communications link after a module reset.

113. A test apparatus as recited in claim 112 wherein said module processor presets said memory element upon completion of said module processor configuration thereby causing a JTAG “

test logic reset”

state which terminates JTAG operation while enabling initiation of a different mode of serial communication via the same said data in, data out, and clock lines.

114. A test apparatus as recited in claim 83 wherein said controller selectively resets one or more of said modules.

115. A test apparatus as recited in claim 114 by selectively forcing respective ones of said clock lines to a consistent state for a predefined amount of time.

116. A test apparatus as recited in claim 114 wherein said controller detects, identifies and configures said one or more reset modules.