Integrated circuit with upstanding stylus

• US 20050127348A1
• Filed: 12/10/2003
• Published: 06/16/2005
• Est. Priority Date: 12/10/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Horak, David V., Lam, Chung H.
• Granted Patent: US 7,943,919 B2
• Time in Patent Office: Days
• US Class Current: 257/3
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8418 adapted for focusing electric field or current, e.g. tip-shaped
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A stylus, an integrated circuit (IC) and method of forming the IC. The stylus extends upward from its apex and has a substantially circular cross section that decreases in diameter upward from the apex. The stylus is formed in a mold that may be formed in an orifice in a dielectric layer between wiring layers. The mold may include multiple concentric layers. For a more pronounced, non-linear stylus taper, each layer may be thinner than its next adjacent outer concentric layer.

Claims

1. A stylus formed on an integrated circuit (IC) said IC including circuits formed on a semiconductor layer wired together in a plurality of wiring layers, said stylus disposed above said semiconductor layer and extending upward from an apex.

2. A stylus as in claim 1, wherein said stylus has a substantially circular horizontal cross section and increases in diameter from said apex.

3. A stylus as in claim 2, wherein said diameter increases non-linearly.

4. A stylus as in claim 1, wherein said stylus is a metal stylus.

5. A stylus as in claim 1, wherein said stylus is a doped semiconductor stylus.

6. A stylus as in claim 1, wherein at least a part of said stylus is contained within a tip mold.

7. A stylus as in claim 7, wherein said tip mold is disposed in a dielectric layer between a pair of said plurality of wiring layers.

8. A stylus as in claim 7, wherein said tip mold comprises a plurality of concentric layers.

9. A stylus as in claim 8, wherein said concentric layers are silicon nitride layers.

10. A stylus as in claim 8, wherein said concentric layers are silicon oxide layers.

11. An integrated circuit (IC) including circuits formed on a semiconductor layer wired together by wires in a plurality of wiring layers, at least one of said circuits including a stylus disposed above said semiconductor layer and extending upward from an apex, said stylus having a substantially circular horizontal cross section and increasing in diameter from said apex.

12. An IC as in claim 11, wherein said stylus increases in diameter non-linearly from said apex.

13. An IC as in claim 12, wherein said stylus is a conductive material.

14. A method of forming an integrated circuit (IC) including at least one stylus, said method comprising the steps of:

a) forming an orifice in a surface layer of a layered wafer;

b) forming a tip mold in said orifice, said tip mold having a circular cross section decreasing in diameter from top to bottom;

c) filling said tip mold with tip material, the tip of a stylus forming in said filled tip mold; and

d) removing excess tip material from an upper surface of said surface layer.

15. A method of forming an IC as in claim 14, wherein the step (b) of forming the tip mold comprises the steps of:

i) forming a conformal layer on a surface layer of said layered wafer;

ii) removing horizontal portions of said conformal layer from said surface layer; and

iii) repeating steps (i) and (ii) until said tip mold is formed.

16. A method of forming an IC as in claim 15, wherein each succeeding said conformal layer is formed thinner than its immediately preceding layer.

17. A method of forming an IC as in claim 16, wherein steps (i) and (ii) are repeated three times, such that a layered tip mold is formed from four concentric spacer layers.

18. A method of forming an IC as in claim 17, wherein the step (ii) of removing horizontal portions comprises etching said conformal layer with a plasma etch having an enhanced sputtering component.

19. A method of forming an IC as in claim 18, wherein the step (ii) of removing horizontal portions comprises biasing said layered wafer during said plasma etch, biasing said layered wafer enhancing sputtering.

20. A method of forming an IC as in claim 19, wherein said layered wafer is self biased.