Function line and transistor array using the same

• US 20050127363A1
• Filed: 11/08/2002
• Published: 06/16/2005
• Est. Priority Date: 12/06/2001
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Sakai, Osamu, Nishiki, Hirohiko, Hatano, Akitsugu
• Granted Patent: US 7,339,192 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/144 Devices controlled by radiation

Abstract

An active-matrix substrate 30 includes multiple function lines 31, a structure for fixing up the arrangement of the function lines, a first conductive layer 43, a second conductive layer 42, multiple transistors 32 and multiple pixel electrodes 33. Each of the function lines 31 includes: a core 36, at least the surface of which has electrical conductivity; an insulating layer 37 that covers the surface of the core; and a semiconductor layer 38 that covers the insulating layer. Some portions of the first and second conductive layers 43 and 42 overlap with the respective semiconductor layers of the function lines but the others not. The transistors 32 are provided so as to have their channel defined as a region 44 in the semiconductor layer by the first and second conductive layers. The pixel electrodes 33 are electrically connected to the first conductive layer 43.

Claims

1-51. -51. (canceled)

52. A function line comprising:

a core, at least the surface of which has electrical conductivity;

a first insulating layer covering the surface of the core;

a semiconductor layer covering the first insulating layer; and

a second insulating layer covering the semiconductor layer.

53. The function line of claim 52, wherein the first insulating layer, the semiconductor layer and the second insulating layer cover the core substantially entirely.

54. The function line of claim 52, wherein the core is made of a metal.

55. The function line of claim 52, wherein the core includes:

an electrically insulating fine wire; and

a conductive layer covering the fine wire.

56. The function line of claim 52, wherein the core has a diameter of 5 μ

m to 1,000 μ

m.

57. The function line of claim 52, wherein the semiconductor layer is made of a transparent semiconductor.

58. The function line of claim 52, further comprising an opaque layer, which is provided so as to cover the second insulating layer.

59. The function line of claim 52, wherein the second insulating layer has light blocking ability.

60. The function line of claim 52, wherein the second insulating layer has a thickness of at least 10 nm.

61. A transistor array comprising:

a plurality of function lines, each including a core, at least the surface of which has electrical conductivity, an insulating layer covering the surface of the core, and a semiconductor layer covering the insulating layer;

a fixing structure for fixing up the relative arrangement of the function lines; and

a plurality of transistors, each including a first conductive layer and a second conductive layer, wherein some portions of the first and second conductive layers overlap with the respective semiconductor layers of the function lines but the others not, and wherein the transistors are provided so as to have their channel defined as a region in the semiconductor layer by the first and second conductive layers.

62. The transistor array of claim 61, wherein the insulating layer and the semiconductor layer cover the core substantially entirely.

63. The transistor array of claim 61, wherein the core is made of a metal.

64. The transistor array of claim 61, wherein the core includes:

an electrically insulating fine wire; and

a conductive layer covering the fine wire.

65. The transistor array of claim 61, wherein the core has a diameter of 5 μ

m to 1,000 μ

m.

66. The transistor array of claim 61, wherein the semiconductor layer is made of a transparent semiconductor.

67. The transistor array of claim 61, further comprising an opaque layer, which is provided so as to cover the semiconductor layer.

68. The transistor array of claim 61, wherein the fixing structure includes a planarizing layer that fills in gaps between the function lines.

69. The transistor array of claim 61, wherein the core has a tensile strength of 100 MPa to 1,000 MPa along its length.

70. The transistor array of claim 61, wherein after the insulating layer and the semiconductor layer have been deposited so as to cover the core, the function lines are fixed up with the fixing structure.

71. The transistor array of claim 61, wherein each said transistor further includes a third conductive layer, which is connected to the second conductive layer, some portions of the third conductive layer overlapping with the semiconductor layer but the others not, the first conductive layer being sandwiched between the second and third conductive layers.

72. The transistor array of claim 70, wherein each of the function lines has a plurality of grooves to divide the semiconductor layer into multiple sections such that the grooves crosses the length of the function line.

95. A semiconductor device comprising the transistor array of claim 61.

73. An active-matrix substrate comprising:

a plurality of function lines, each including a core, at least the surface of which has electrical conductivity, an insulating layer covering the surface of the core, and a semiconductor layer covering the insulating layer;

a fixing structure for fixing up the relative arrangement of the function lines;

a plurality of transistors, each including a first conductive layer and a second conductive layer, wherein some portions of the first and second conductive layers overlap with the respective semiconductor layers of the function lines but the others not, and wherein the transistors are provided so as to have their channel defined as a region in the semiconductor layer by the first and second conductive layers; and

a plurality of pixel electrodes, which are electrically connected to the first conductive layer.

74. The active-matrix substrate of claim 73, wherein the insulating layer and the semiconductor layer cover the core substantially entirely.

75. The active-matrix substrate of claim 73, wherein the core is made of a metal.

76. The active-matrix substrate of claim 73, wherein the core includes:

an electrically insulating fine wire; and

a conductive layer covering the fine wire.

77. The active-matrix substrate of claim 73, wherein the core has a diameter of 5 μ

m to 1,000 μ

m.

78. The active-matrix substrate of claim 73, wherein the semiconductor layer is made of a transparent semiconductor.

79. The active-matrix substrate of claim 73, wherein the core has a tensile strength of 100 MPa to 1,000 MPa along its length.

80. The active-matrix substrate of claim 73, wherein after the insulating layer and the semiconductor layer have been deposited so as to cover the core, the function lines are fixed up with the fixing structure.

81. The active-matrix substrate of claim 73, wherein each said transistor further includes a third conductive layer, which is connected to the second conductive layer, some portions of the third conductive layer overlapping with the semiconductor layer but the others not, the first conductive layer being sandwiched between the second and third conductive layers.

82. The active-matrix substrate of claim 81, wherein each of the function lines has a plurality of grooves to divide the semiconductor layer into multiple sections such that the grooves crosses the length of the function line.

83. The active-matrix substrate of claim 73, wherein the fixing structure includes a planarizing layer that fills in gaps between the function lines.

84. The active-matrix substrate of claim 73, wherein the fixing structure includes a base substrate and an adhesive layer, the function lines being bonded onto the base substrate with the adhesive layer.

85. The active-matrix substrate of claim 84, wherein the base substrate has a plurality of grooves on the surface thereof, at least some of the function lines being bonded onto the base substrate with the adhesive layer so as to be embedded in the grooves.

86. The active-matrix substrate of claim 85, wherein the adhesive layer includes a light blocking substance.

87. The active-matrix substrate of claim 85, wherein the planarizing layer includes a light blocking substance.

88. The active-matrix substrate of claim 73, further comprising a plurality of storage capacitor lines, each including a core, the surface of which is electrically conductive, and an insulating layer covering the surface of the core, the storage capacitor lines overlapping with each other under the pixel electrodes.

89. The active-matrix substrate of claim 73, wherein substrate is made of a plastic with elasticity.

90. The active-matrix substrate of claim 73, wherein the second conductive layer is a data line.

91. The active-matrix substrate of claim 73, wherein the second conductive layer is a reference potential supply line.

96. A display device comprising:

the active-matrix substrate of claim 73;

a counter substrate; and

a display medium layer sandwiched between the substrates.

92. An active-matrix substrate comprising:

a pixel region including a plurality of pixel electrodes; and

a driver circuit for driving the pixels,

wherein the driver circuit includes;

a p-type function line with a PMOS transistor, the PMOS transistor including a core, a semiconductor layer covering the surface of the core, an insulating layer covering the semiconductor layer, and at least one gate electrode on the surface of the insulating layer and having a p-channel defined in the semiconductor layer by the gate electrode;

an n-type function line with an NMOS transistor, the NMOS transistor including a core, a semiconductor layer covering the surface of the core, an insulating layer covering the semiconductor layer, and at least one gate electrode on the surface of the insulating layer and having an n-channel defined in the semiconductor layer by the gate electrode;

a fixing structure for fixing up the relative arrangement of the p-type and n-type function lines; and

an interconnect for connecting the PMOS and NMOS transistors together so as to make a CMOS device.

94. The active-matrix substrate of claim 92, wherein the pixel region includes:

a plurality of function lines, each including a core, at least the surface of which has electrical conductivity, an insulating layer covering the surface of the core, and a semiconductor layer covering the insulating layer;

a fixing structure for fixing up the relative arrangement of the function lines;

a plurality of transistors, each including a first conductive layer and a second conductive layer, wherein some portions of the first and second conductive layers overlap with the respective semiconductor layers of the function lines but the others not, and wherein the transistors are provided so as to have their channel defined as a region in the semiconductor layer by the first and second conductive layers; and

a plurality of pixel electrodes, which are electrically connected to the first conductive layer.

93. An active-matrix substrate comprising:

a pixel region including a plurality of pixel electrodes; and

a driver circuit for driving the pixels,

wherein the driver circuit includes;

a foil substrate; and

an NMOS transistor and a PMOS transistor, which are held on the foil substrate and connected together so as to make a CMOS device.

97. A method for fabricating a transistor array, the method comprising the steps of:

preparing a plurality of function lines, each including a core, at least the surface of which has electrical conductivity, an insulating layer covering the surface of the core, and a semiconductor layer covering the insulating layer;

fixing up the relative arrangement of the function lines with a fixing structure; and

providing a first conductive layer and a second conductive layer such that some portions of the first and second conductive layers overlap with the respective semiconductor layers of the function lines but the others not, thereby forming a plurality of transistors having their channel defined as a region in the semiconductor layer by the first and second conductive layers.

98. A method for fabricating an active-matrix substrate, the method comprising the steps of:

preparing a plurality of function lines, each including a core, at least the surface of which has electrical conductivity, an insulating layer covering the surface of the core, and a semiconductor layer covering the insulating layer;

fixing up the relative arrangement of the function lines with a fixing structure;

providing a first conductive layer and a second conductive layer such that some portions of the first and second conductive layers overlap with the respective semiconductor layers of the function lines but the others not, thereby forming a plurality of transistors having their channel defined as a region in the semiconductor layer by the first and second conductive layers; and

forming a plurality of pixel electrodes, which are electrically connected to the first conductive layer of the transistors.

99. The active-matrix substrate fabricating method of claim 98, wherein the first conductive layer of the transistors and the pixel electrodes are formed simultaneously.

100. The active-matrix substrate fabricating method of claim 98, wherein the step of fixing the arrangement includes the steps of:

bonding the function lines onto the base substrate with an adhesive layer; and

filling in gaps between the function lines with a planarizing layer at least partially.

101. The active-matrix substrate fabricating method of claim 98, further comprising the step of preparing a plurality of storage capacitor lines, each including a core, the surface of which is electrically conductive, and an insulating layer covering the surface of the core,

wherein the step of fixing the arrangement includes the steps of:

pressing the function lines and the storage capacitor lines onto a plastically deformable layer, thereby embedding the function and storage capacitor lines to a predetermined depth in the plastically deformable layer;

burying portions of the function and storage capacitor lines, which are exposed over the plastically deformable layer, in a curable resin on the base substrate; and

curing the curable resin and then removing the plastically deformable layer.

102. A method for fabricating an active-matrix substrate, the method comprising the steps of

preparing a p-type function line and an n-type function line and fixing up the arrangement of the p-type and n-type function lines, wherein the p-type function line includes a PMOS transistor, which includes:

a core;

a semiconductor layer covering the surface of the core;

an insulating layer covering the semiconductor layer; and

at least one gate electrode on the surface of the insulating layer and which has a p-channel defined in the semiconductor layer by the gate electrode, and wherein -the n-type function line includes an NMOS transistor, which includes;

a core;

a semiconductor layer covering the surface of the core;

an insulating layer covering the semiconductor layer; and

at least one gate electrode on the surface of the insulating layer and which has an n-channel defined in the semiconductor layer by the gate electrode, and

forming an interconnect that connects the PMOS and NMOS transistors together so as to make a CMOS device.