Carrier layer for a semiconductor layer sequence and method for producing semiconductor chips

• US 20050127382A1
• Filed: 11/29/2004
• Published: 06/16/2005
• Est. Priority Date: 11/28/2003
• Status: Active Grant

• Current Assignee: OSRAM OLED GMBH (Ams-Osram AG)
• Original Assignee: Osram Opto Semiconductors GmbH (Ams-Osram AG)
• Inventors: Groetsch, Stefan, Ploessl, Andreas, Hahn, Berthold, Illek, Stefan
• Granted Patent: US 7,723,730 B2
• Time in Patent Office: Days
• US Class Current: 257/94
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/83048 Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 33/007 : comprising nitride compounds
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01L 33/641 : characterized by the materials
• CPC Class Codes: H01L 33/647 : the elements conducting electric current to or from the semiconductor body

Abstract

A carrier layer (1) for a semiconductor layer sequence comprising an electrical insulation layer (2) containing AlN or a ceramic. Furthermore a method for producing semiconductor chips is described.

Claims

1. A carrier layer (1) for a semiconductor layer sequence (7), the carrier layer (1) comprising an electrical insulation layer (2),

wherein

the insulation layer (2) contains AlN.

2. The carrier layer (1) as claimed in claim 1,

wherein

the insulation layer contains an AlN ceramic.

4. The carrier layer (1) as claimed in claim 1 or 3,

wherein

the insulation layer (2) is formed in self-supporting fashion.

5. The carrier layer (1) as claimed in claim 1 or 3,

wherein

the carrier layer (1) has a conductor structure.

6. The carrier layer (1) as claimed in claim 5,

wherein

the carrier layer (1) has a first and a second main area and the conductor structure extends from the first (5) to the second main area (6).

7. The carrier layer (1) as claimed in claim 5,

wherein

the conductor structure is at least partly formed in cutouts (3) of the insulation layer (2) that reach from the first to the second main area of the carrier layer (1).

8. The carrier layer (1) as claimed in claim 5,

wherein

the semiconductor layer sequence (7) is electrically conductively connected to the conductor structure.

9. The carrier layer (1) as claimed in claim 5,

wherein

the conductor structure contains a metal.

10. The carrier layer (1) as claimed in claim 9,

wherein

the conductor structure contains W, Ag, Au, Cu or an alloy having at least one of said materials.

11. The carrier layer (1) as claimed in claim 5,

wherein

a thermally conductive substance (11) for increasing the thermal conductivity is at least partly introduced into the conductor structure.

12. The carrier layer (1) as claimed in claim 5,

wherein

the semiconductor layer sequence (7) has a radiation-generating active zone (10).

13. The carrier layer (1) as claimed in claim 12,

wherein

a mirror layer (9) is arranged downstream of the active zone (10).

14. The carrier layer (1) as claimed in claim 13,

wherein

the mirror layer (9) is electrically conductively connected to the semiconductor layer sequence (7).

15. The carrier layer (1) as claimed in claim 13,

wherein

the mirror layer (9) is arranged between the first main area of the carrier layer (1) and the active zone (10).

16. The carrier layer (1) as claimed in claim 1 or 3,

wherein

the semiconductor layer sequence is formed for LED chips or radiation-emitting components with a resonator, in particular edge-emitting lasers or vertically emitting components, including VCSEL, VECSEL and RCLEDs.

17. The carrier layer (1) as claimed in claim 1 or 3,

wherein

the semiconductor layer sequence (7) contains at least one III-V semiconductor material, comprising In_xGa_yAl_1-x-yP, In_xGa_yAl_1-x-yN or In_xGa_yAl_1-x-yAs, in each case where O≦

x≦

1, 0≦

y≦

1 and x+y≦

1.

3. A carrier layer (1) for a semiconductor layer sequence (7), the carrier layer (1) comprising an electrical insulation layer (2),

wherein

the insulation layer (2) contains a ceramic.

18. A method for producing semiconductor chips (15) with a semiconductor chip region (12) that has a radiation-generating active zone (10) and is arranged on a chip carrier (101) containing AlN, featuring the following steps:

provision of a semiconductor layer sequence (7) with the radiation-emitting active zone on a substrate (16),

connection of the semiconductor layer sequence (7) to a carrier layer (1) containing AlN,

removal of the substrate (16),

patterning of the semiconductor layer sequence (7) into semiconductor chip regions (12),

singulation of the structure with semiconductor chip regions (12) and carrier layer (1) into semiconductor chips (15) that each comprise at least one semiconductor chip region (12) and are arranged on a chip carrier (101) that emerges from the carrier layer (1) as a result of the singulation.

20. The method as claimed in claim 18 or 19,

wherein

the carrier layer (1) has a conductor structure.

21. The method as claimed in claim 18 or 19,

wherein

the carrier layer (1) has a first (5) and a second main area (7) and the conductor structure extends from the first to the second main area.

22. The method as claimed in claim 18 or 19,

wherein

the conductor structure is electrically conductively connected to the semiconductor sequence (7).

23. The method as claimed in claim 18 or 19,

wherein

a mirror layer (9) is arranged between the carrier layer (1) and the semiconductor layer sequence (7).

24. The method as claimed in claim 18 or 19,

wherein

the conductor structure is configured such that essentially each semiconductor chip (15) is electrically conductively connected to the conductor structure after singulation.

19. A method for producing semiconductor chips (15) with a semiconductor chip region (12) that has a radiation-generating active zone (10) and is arranged on a chip carrier (101) containing a ceramic, featuring the following steps:

provision of a semiconductor layer sequence (7) with the radiation-emitting active zone on a substrate (16),

connection of the semiconductor layer sequence (7) to a carrier layer (1) containing a ceramic,

removal of the substrate (16),

patterning of the semiconductor layer sequence (7) into semiconductor chip regions (12),

singulation of the structure with semiconductor chip regions (12) and carrier layer (1) into semiconductor chips (15) that each comprise at least one semiconductor chip region (12) and are arranged on a chip carrier (101) that emerges from the carrier layer (1) as a result of the singulation.