Semiconductor assembly with conductive rim and method of producing the same

• US 20050127525A1
• Filed: 12/15/2003
• Published: 06/16/2005
• Est. Priority Date: 12/15/2003
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Wachtmann, Bruce K., Judy, Michael, Alie, Susan A., Kneedler, David
• Granted Patent: US 7,034,393 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: Y10S 257/924 with passive device, e.g. capacitor, or battery, as integral part of housing or housing element, e.g. cap

Abstract

An apparatus has first and second wafers, and a conductive rim between the first and second wafers. The conductive rim electrically and mechanically connects the first and second wafers. In addition, the conductive rim and second wafer at least in part seal an area on the surface of the first wafer.

Claims

1. An apparatus comprising:

a first wafer;

a second wafer; and

a conductive rim between the first and second wafers, the conductive rim electrically and mechanically connecting the first and second wafers, the conductive rim and second wafer at least in part sealing an area on the surface of the first wafer.

2. The apparatus as defined by claim 1 wherein the conductive rim and second wafer hermetically seal the area on the surface of the first wafer.

3. The apparatus as defined by claim 1 wherein the conductive rim comprises a silicide.

4. The apparatus as defined by claim 1 wherein the area on the first wafer includes MEMS structure.

5. The apparatus as defined by claim 4 wherein the conductive rim is electrically isolated from the MEMS structure.

6. The apparatus as defined by claim 4 wherein the second wafer includes a cap.

7. The apparatus as defined by claim 1 wherein the first wafer includes circuitry capable of delivering a bias voltage to the second wafer via the conductive rim.

8. The apparatus as defined by claim 7 wherein the circuitry has a maximum temperature to which it can be exposed, the conductive rim being produced from a material that interdiffuses or melts at a temperature that is less than the maximum temperature to which the circuitry can be exposed.

9. The apparatus as defined by claim 1 wherein at least one of the first wafer and the second wafer comprises a silicon based material.

10. The apparatus as defined by claim 1 wherein at least one of the first wafer and the second wafer is comprised of polysilicon, single crystal silicon, or silicon germanium.

11. A MEMS device comprising:

a first wafer;

a second wafer; and

conductive and sealing means between the first and second wafers, the conductive and sealing means electrically and mechanically connecting the first and second wafers, the second wafer and the conductive and sealing means at least in part sealing an area on the surface of the first wafer.

12. The MEMS device as defined by claim 11 wherein the conductive and sealing means includes a silicide bond between the first and second wafers.

13. The MEMS device as defined by claim 11 further including means for applying a bias voltage to the second wafer through the conductive and sealing means, the applying means being on the first wafer.

14. A method of forming a MEMS device, the method comprising:

placing rim material between a first wafer and a second wafer to form an intermediate apparatus, the rim material forming a closed loop defining an area on the first wafer;

applying pressure to the intermediate apparatus; and

heating the intermediate apparatus,

after heating and applying pressure, the rim material cooperating with the first and second wafers to seal the area on the first wafer and electrically connect the first and second wafers.

15. The method as defined by claim 14 wherein the second wafer is substantially parallel with the first wafer.

16. The method as defined by claim 14 wherein the rim material cooperates with the first and second wafers by integrating with the first and second wafers to form a composite material comprising the rim material.

17. The method as defined by claim 14 wherein the rim material diffuses into the first and second wafers to form a silicide material.

18. The method as defined by claim 14 further comprising:

forming MEMS structure within the area on the first wafer.

19. The method as defined by claim 14 further comprising forming circuitry on the first wafer capable of applying a bias voltage to the second wafer through the rim material.

20. A MEMS device formed by the method defined by claim 14.