Multi-state NROM device

• US 20050128804A1
• Filed: 05/10/2004
• Published: 06/16/2005
• Est. Priority Date: 12/16/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Granted Patent: US 7,050,330 B2
• Time in Patent Office: Days
• US Class Current: 365/185.10
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An array of NROM flash memory cells configured to store at least two bits per four F². Split vertical channels are generated along each side of adjacent pillars. A single control gate is formed over the pillars and in the trench between the pillars. The split channels can be connected by an n+ region at the bottom of the trench or the channel wrapping around the trench bottom. Each gate insulator is capable of storing a charge that is adequately separated from the other charge storage area due to the increased channel length.

Claims

1. A multi-state NROM transistor comprising:

a substrate having a plurality of vertical pillars, each pillar comprising an upper doped region;

a gate insulator layer formed along facing sides of a first pillar and a second pillar of the plurality of vertical pillars;

a control gate formed overlying the gate insulator layers and the pillars; and

a lower doped region formed under a trench located between the first and second pillars, wherein during transistor operation the lower doped region couples a first channel that forms along the facing side of the first pillar and a second channel that forms along the facing side of the second pillar.

2. The transistor of claim 1 wherein the upper and lower doped regions are n+ doped regions in a p-type substrate and the upper doped region is located substantially at the top of each pillar.

3. The transistor of claim 1 wherein the lower doped region is not coupled to an electrical contact.

4. The transistor of claim 1 wherein the transistor operates as equivalent to a transistor having a size of less than 1.0 lithographic feature squared (1F²).

5. The transistor of claim 1 wherein each gate insulator defines a charge storage region.

6. The transistor of claim 1 wherein the first and second channels are formed between the upper doped region and the lower doped region during a program operation.

7. The transistor of claim 1 wherein the gate insulator layer is comprised of an oxide—

nitride—

oxide composite structure.

8. The transistor of claim 1 wherein the gate insulator layer is comprised of a composite structure of one of:

oxide—

nitride—

aluminum oxide, oxide—

aluminum oxide—

oxide, or oxide—

silicon oxycarbide—

oxide.

9. The transistor of claim 1 wherein the gate insulator layer is comprised of one of the following non-composite structures:

silicon oxides formed by wet oxidation and not annealed, silicon rich oxides with inclusions of nanoparticles of silicon, silicon oxynitride layer, silicon rich aluminum oxide insulators, silicon oxycarbide insulators, or silicon oxide insulators with inclusions of nanoparticles of silicon carbide.

10. The transistor of claim 1 wherein the gate insulator layer is comprised of a non-stoichiometric single layer.

11. The transistor of claim 10 wherein the non-stoichiometric single layer comprises one of Si, N, Al, Ti, Ta, Hf, or La.

12. An array of multi-state NROM transistors comprising:

a substrate having a plurality of vertical pillars each separated by a trench, each pillar comprising an upper doped region, each upper doped region coupled to a first bitline of the array;

a plurality of gate insulator layers, each layer formed along facing sides of adjacent pillars of the plurality of vertical pillars;

a control gate formed in the trenches and overlying the plurality of vertical pillars, the control gate forming a wordline between a row of NROM transistors of the array of multi-state NROM transistors; and

a plurality of lower doped regions, each region formed under each trench, wherein during operation of the transistors each lower doped region couples a first channel that forms in a first pillar along a first side of a first trench and a second channel that forms in a second pillar along a second side of the first trench, each lower doped region coupled to a second bitline of the array.

13. The transistor of claim 12 wherein the substrate is comprised of a silicon material and the control gate is comprised of a polysilicon.

14. The transistor of claim 12 wherein the plurality of lower doped regions are not accessible by electrical contacts.

15. The transistor of claim 12 wherein the gate insulator is comprised of one of a composite structure or a non-stoichiometric single layer.

16. The transistor of claim 12 wherein, during transistor operation, the first and second channels act as series coupled transistors having at least two charge storage areas.

17. An electronic system comprising:

a processor circuit that generates memory control signals; and

an NROM flash memory device coupled to the processor circuit, the flash memory device having a plurality of multi-state NROM transistors, each transistor comprising;

a substrate having a plurality of vertical pillars, each pillar comprising an upper doped region and separated by a trench from adjacent pillars;

a first gate insulator layer formed along a first side of a first trench;

a second gate insulator layer formed along a second opposing side of the first trench;

a control gate formed in the first trench and overlying the plurality of vertical pillars; and

a lower doped region formed under the first trench, wherein during transistor operation the lower doped region couples a first channel that forms adjacent to the first gate insulator and a second channel that forms adjacent to the second gate insulator.

18. The system of claim 17 wherein during operation of the transistor, the first and second gate insulators each comprise a charge storage area.

19. The system of claim 17 wherein the first and second gate insulator layers are comprised of an oxide—

nitride—

oxide composite.

20. The system of claim 17 wherein an upper doped region of a first pillar adjacent the first trench acts as a drain region and an upper doped region of a second pillar adjacent the first trench acts as a source region.

21. A multi-state NROM transistor comprising:

a substrate having a plurality of vertical pillars, each pillar comprising a doped region;

a gate insulator layer formed along facing sides of a first pillar and a second pillar of the plurality of vertical pillars; and

a control gate formed overlying the gate insulator layers and the pillars wherein during transistor operation a channel forms between a doped region of the first pillar and the doped region of the second pillar.

22. The transistor of claim 21 wherein during transistor operation a first doped region operates as a source region and a second doped region operates a drain region.

23. The transistor of claim 21 wherein the transistor operation is a programming operation.

24. An array of multi-state NROM transistors comprising:

a substrate having a plurality of vertical pillars with a trench between each pillar, each pillar comprising a doped region;

a plurality of gate insulator layers, each layer formed along opposing sides of each trench; and

a control gate formed in each trench and overlying the plurality of vertical pillars to form a wordline wherein during transistor operation a channel forms between a doped region of the first pillar and the doped region of the second pillar.

25. The array of claim 24 wherein the doped regions are coupled to bitlines that underlie and are substantially perpendicular to the wordline.

26. A method for manufacturing a split-channel transistor, the method comprising:

incising a substrate to form a plurality of trenches, each pair of trenches defining a pillar;

doping a region in an upper portion of each pillar;

doping a lower region under each trench;

forming a nitride storage region on each facing side of adjacent pillars; and

forming a control gate overlying the pillars and in the plurality of trenches wherein during a programming operation of the transistor, a channel is formed along the facing sides of adjacent pillars and are connected by the lower doped region, the lower doped region not being coupled to an electrical contact.

27. The method of claim 26 and further including forming a dielectric material in each trench between the substrate and the control gate.

28. The method of claim 26 wherein the control gate is polysilicon.

29. The method of claim 26 wherein the split-channel transistor forms two field effect transistors connected in series.

30. The method of claim 26 wherein a first doped region in a first pillar is a drain region and a second doped region in a second, adjacent pillar is a source region.

31. The method of claim 26 wherein the doping comprises creating n+ regions in a p-type substrate.

32. A method for programming a split-channel having a pair of pillars forming a trench, each pillar having a source/drain region and the trench having a floating n+ diffusion region that has no electrical contact, nitride charge storage regions formed along facing sides of the trench and a control gate overlying the nitride charge storage regions and the pair of pillars, the method comprising:

grounding a first source/drain region;

applying a gate voltage to the control gate; and

applying a drain voltage to a second source/drain region such that a channel forms along the facing sides of the trench between the first and second source/drain regions and under the trench.

33. The method of claim 32 wherein the channels along each side of the trench are connected by the floating n+ diffusion region.

34. A method for programming a split-channel having a pair of pillars forming a trench, each pillar having a source/drain region, nitride charge storage regions formed along facing sides of the trench and a control gate overlying the nitride charge storage regions and the pair of pillars, the method comprising:

grounding a first source/drain region;

applying a gate voltage to the control gate; and

applying a drain voltage to a second source/drain region such that a channel forms along the facing sides of the trench between the first and second source/drain regions and under the trench.

35. A method for manufacturing a split-channel transistor, the method comprising:

incising a substrate to form a plurality of trenches, each pair of trenches defining a pillar;

doping a region in an upper portion of each pillar;

forming a nitride storage region on each facing side of adjacent pillars; and

forming a control gate overlying the pillars and in the plurality of trenches wherein during a programming operation of the transistor, a channel is formed along the facing sides of adjacent pillars and are connected together under each trench.