Semiconductor data processing device

• US 20050128815A1
• Filed: 12/03/2004
• Published: 06/16/2005
• Est. Priority Date: 12/09/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Tanaka, Toshihiro, Yamaki, Takashi, Kato, Akira, Umemoto, Yukiko, Ishikawa, Jiro
• Granted Patent: US 7,110,295 B2
• Time in Patent Office: Days
• US Class Current: 365/185.290
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

An erasing current is distributed to reduce a load of an internal power circuit and to decrease the number of drivers for erase. A semiconductor data processing device has: a memory array having nonvolatile memory cells arrayed in a matrix and divided into a plurality of erase blocks each instructed to be erased together; and a control circuit, wherein the control circuit controls both of two kinds of erasing voltages applied to the nonvolatile memory cell in the erase block instructed to be erased together to select an erase sector from the erase block for performing erase for each erase sector, thereby performing the erase for each erase sector in time division. Time division erase can distribute an erasing current. Two kinds of erasing voltages are used to select the erase sector. No specific drivers need be provided for each erase sector.

Claims

1. A semiconductor data processing device comprising:

a memory array having nonvolatile memory cells arrayed in a matrix and divided into a plurality of erase blocks each instructed to be erased together; and

a control circuit,

wherein said control circuit controls both of two kinds of erasing voltages applied to the nonvolatile memory cell in the erase block instructed to be erased together to select an erase sector from the erase block for performing erase for each erase sector, thereby performing said erase for each erase sector in time division.

2. The semiconductor data processing device according to claim 1, wherein two kinds of erasing voltage driving drivers applying two kinds of erasing voltages to said nonvolatile memory cell shareably drive a plurality of sectors, respectively.

3. The semiconductor data processing device according to claim 1, wherein said nonvolatile memory has a source, a drain, a channel, a control gate arranged over the channel on said source side and a charge storage region and a memory gate stacked over the channel on said drain side to be electrically insulated from each other, and a dielectric breakdown seen from said control gate is lower than that seen from said memory gate.

4. The semiconductor data processing device according to claim 2, further comprising a switch MOS transistor which can selectively connect a bit line connected to said drain to a global bit line,

wherein the gate breakdown voltage of said switch MOS transistor is lower than that seen from said memory gate of said nonvolatile memory cell.

5. The semiconductor data processing device according to claim 4, further comprising a first driver driving a control gate control line connected to said control gate, a second driver driving a memory gate control line connected to said memory gate, a third driver driving said switch MOS transistor to an ON state, and a fourth driver driving a source line connected to said source,

wherein said second and fourth drivers are said two kinds of erasing voltage driving drivers at erase, and

wherein said first and third drivers use a first voltage as an operating power source and said second and fourth drivers use a voltage higher than said first voltage as an operating power source.

6. The semiconductor data processing device according to claim 5, wherein said control circuit, when increasing a threshold voltage of the nonvolatile memory cell seen from said memory gate by write, uses the operating power source of the first driver as the first voltage, the operating power source of the fourth driver as a second voltage higher than the first voltage, and the operating power source of the second driver as a third voltage higher than the second voltage, thereby injecting hot electrons from a bit line electrode side to the charge storage region.

7. The semiconductor data processing device according to claim 6, wherein said control circuit, when decreasing the threshold voltage of the nonvolatile memory cell seen from said memory gate by erase, uses the operating power source of said second driver as a fourth voltage lower than the third voltage, and the operating power source of said fourth driver as a fifth voltage higher than the second voltage, thereby injecting holes to the charge storage region to make electrons disappear.

8. The semiconductor data processing device according to claim 6, wherein said control circuit, when reading stored information from said nonvolatile memory cell, uses the operating power source of the first driver as the first voltage.

9. The semiconductor data processing device according to claim 7, wherein said first and third drivers input an address decode signal to select operation, and said second and fourth drivers input an output of the first driver to select operation.

10. The semiconductor data processing device according to claim 9, wherein said first and third drivers are arranged on one side across the array of said nonvolatile memory cells, and said second and fourth drivers are arranged on another side.

11. The semiconductor data processing device according to claim 5, further comprising a logic operating unit performing logic operation using said first voltage as an operating power source.