Methods and apparatus for improved memory access

• US 20050128823A1
• Filed: 01/10/2005
• Published: 06/16/2005
• Est. Priority Date: 10/31/2002
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: Ring Technology Enterprises of Texas LLC (IPNav)
• Inventors: Lynch, William Thomas, Herbison, David James
• Granted Patent: US 7,313,035 B2
• Time in Patent Office: Days
• US Class Current: 365/189.120
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G11C 2029/3202 Scan chain
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/32 Serial access; Scan testing
• CPC Class Codes: G11C 7/1036 using data shift registers

Abstract

A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.

Claims

1. An apparatus, comprising:

at least one memory device having one or more outputs;

at least one set of shift registers interconnected in series, wherein at least one of the shift registers receives a clock signal having a shift frequency, and wherein the shift register is capable of shifting data loaded into the shift register to a next one of the shift registers in the set according to the shift frequency; and

wherein data from one or more of the outputs of the memory device is loaded into a corresponding shift register in one of the sets of shift registers and the loaded data is shifted from the shift register to a next one of the shift registers in the set according to the clock signal, such that the shift register maintains its shift frequency during any loading of the data.

2-54. -54. (canceled)