Semiconductor device including multi-chip

• US 20050128853A1
• Filed: 01/19/2005
• Published: 06/16/2005
• Est. Priority Date: 05/26/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Ayukawa, Kazushige, Miura, Seiji, Saitou, Yoshikazu
• Granted Patent: US 7,554,872 B2
• Time in Patent Office: Days
• US Class Current: 365/230.30
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40607 Refresh operations in memory devices with an internal cache or data buffer
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H01L 2224/06145 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/06156 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48139 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01055 : Cesium [Cs]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

Claims

1-19. -19. (canceled)

20. A semiconductor device comprising:

a first memory array including a plurality of dynamic type memory cells; and

a memory controller receiving signals using a SRAM system and accessing the first memory array by converting the signals,

wherein the memory controller has a temperature measuring module and changes a refresh interval of the first memory array according to the temperature detected by the temperature measurement module.

21. A semiconductor device according to claim 20,

wherein the memory controller further has a refresh counter,

wherein the refresh counter generates a refresh address according to the refresh interval of the first memory array and changes the refresh interval in response to an output signal of the temperature measuring module.

22. A semiconductor device according to claim 20,

wherein the memory controller and first memory array are formed on a chip.

23. A semiconductor device according to claim 21,

wherein the memory controller further has an address transition detector circuit detecting transitions in the address signals and the command signals and outputting a pulse indicating the transitions in the address signals and an access controller converting a received address to an address for the first memory array and outputting the address for the first memory array to the first memory array.

24. A semiconductor device according to claim 20, further comprising:

a second memory array including a plurality of static type memory cells,

wherein the first memory array, the second memory array, and the memory controller are incorporated into a package.

25. A semiconductor device according to claim 24,

wherein the memory controller and first memory array are formed on a chip.