Two-wire interface in which a master component monitors the data line during the preamble generation phase for synchronization with one or more slave components

• US 20050128962A1
• Filed: 03/31/2004
• Published: 06/16/2005
• Est. Priority Date: 12/15/2003
• Status: Active Grant

• Current Assignee: II-VI Delaware, Inc. (Coherent Corp.)
• Original Assignee: Finisar Corporation (II-VI Incorporated)
• Inventors: Hahin, Jayne C., Dybsetter, Gerald L.
• Granted Patent: US 8,667,194 B2
• Time in Patent Office: Days
• US Class Current: 370/278
• CPC Class Codes: H04J 3/0602 Systems characterised by the synchronising information used

Abstract

A two-wire interface in which upon determining that an operation is to be performed on a slave component, the master component monitors the data wire for a predetermined number of consecutive bits having a particular binary value. Upon detection such a sequence, the master component asserts a frame of a two-wire interface on the data wire. This detected predetermined number of consecutive bits will be considered to be the preamble. During at least some of the preamble phase, the master component is not asserting anything on the data wire. Instead, the data wire is pulled high (or low) by a weak pull-up (or pull-down) resistor. Furthermore, the frame is designed so that there are bits having a guaranteed binary value that is opposite what would be expected in the preamble, to thereby facilitate synchronization.

Claims

1. In a system that includes a master component that is configured to communicate with one or more slave components over a clock wire and a data wire, a method for the master component communicating over the data wire while enabling recovery of synchronization between the master component and the one or more slave components, the method comprising the following:

an act of determining that an operation is to be performed on a slave component of the one or more slave components;

an act of monitoring the data wire of the two-wire interface upon determining that the operation is to be performed on the slave component;

an act of detecting at least the predetermined number of consecutive bits of the same binary polarity have occurred on the data wire during the act of monitoring the data wire; and

an act of asserting a frame of a two-wire interface on the data wire in response to the act of detecting that the predetermined number of consecutive bits of the same polarity have occurred on the data wire.

2. A method in accordance with claim 1, wherein the two-wire interface is a guaranteed header two-wire interface.

3. A method in accordance with claim 1, wherein the two-wire interface is not a 0<

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guaranteed header two-wire interface.

4. A method in accordance with claim 1, wherein the act of detecting at least the predetermined number of consecutive bits comprises the following:

an act of detecting at least the predetermined number of consecutive bits of a logical one.

5. A method in accordance with claim 4, wherein the data wire is pulled high when no components are asserting binary values on the data wire.

6. A method in accordance with claim 1, wherein the act of detecting at least the predetermined number of consecutive bits comprises the following:

an act of detecting at least the predetermined number of consecutive bits of a logical zero.

7. A method in accordance with claim 6, wherein the data wire is pulled low when no components are asserting binary values on the data wire.

8. A method in accordance with claim 1, further comprising the following:

an act of the master component asserting a clock signal on the clock wire during at least some of the act of monitoring the data wire.

9. A method in accordance with claim 1, further comprising the following:

an act of the master component asserting a voltage level on the data wire during only a portion of the act of monitoring.

10. A method in accordance with claim 9, wherein the data wire is pulled high when no components are asserting binary values on the data wire.

11. A method in accordance with claim 9, wherein the data wire is pulled low when no components are asserting binary values on the data wire.

12. A method in accordance with claim 1, further comprising the following:

an act of the master component refraining from asserting a voltage level on the data wire during the act of monitoring.

13. A method in accordance with claim 12, wherein the data wire is pulled high when no components are asserting binary values on the data wire.

14. A method in accordance with claim 12, wherein the data wire is pulled low when no components are asserting binary values on the data wire.

15. A method in accordance with claim 1, wherein the act of determining that an operation is to be performed on a slave component of the one or more slave components comprises the following:

an act of determining that a read operation is to be performed with an extended address as compared to other frames communicated over the data wire.

16. A method in accordance with claim 1, wherein the act of determining that an operation is to be performed on a slave component of the one or more slave components comprises the following:

an act of determining that a write operation is to be performed with an extended address as compared to other frames communicated over the data wire.

17. A method in accordance with claim 1, wherein the act of determining that an operation is to be performed on a slave component of the one or more slave components comprises the following:

an act of determining that a read operation is to be performed with a shorter address as compared to other frames communicated over the data wire.

18. A method in accordance with claim 1, wherein the act of determining that an operation is to be performed on a slave component of the one or more slave components comprises the following:

an act of determining that a write operation is to be performed with a shorter address as compared to other frames communicated over the data wire.

19. A method in accordance with claim 1, wherein the act of determining that an operation is to be performed on a slave component of the one or more slave components comprises the following:

an act of determining that a read operation is to be performed with cyclic redundancy checking over the data wire.

20. A method in accordance with claim 1, wherein the act of determining that an operation is to be performed on a slave component of the one or more slave components comprises the following:

an act of determining that a write operation is to be performed with cyclic redundancy checking over the data wire.

21. A method in accordance with claim 1, wherein the act of determining that an operation is to be performed on a slave component of the one or more slave components comprises the following:

an act of determining that a read operation is to be performed with acknowledgements over the data wire.

22. A method in accordance with claim 1, wherein the act of determining that an operation is to be performed on a slave component of the one or more slave components comprises the following:

an act of determining that a write operation is to be performed with acknowledgements over the data wire.

23. A system comprising the following:

a master component;

a slave component;

a clock wire interconnected between the master component and the slave component;

a data wire interconnected between the master component and the slave component,

wherein the master component is configured to perform the following;

an act of determining that an operation is to be performed on the slave component;

an act of monitoring the data wire of the two-wire interface upon determining that the operation is to be performed on the slave component;

an act of detecting at least the predetermined number of consecutive bits of the same binary polarity have occurred on the data wire during the act of monitoring the data wire; and

an act of asserting a frame of a two-wire interface on the data wire in response to the act of detecting that the predetermined number of consecutive bits of the same polarity have occurred on the data wire.

24. A system in accordance with claim 23, wherein the two-wire interface is a guaranteed header two-wire interface.

25. A system in accordance with claim 23, wherein the two-wire interface is not a guaranteed header two-wire interface.

26. A system in accordance with claim 23, wherein the data wire is pulled high when no components are asserting binary values on the data wire.

27. A system in accordance with claim 23, wherein the data wire is pulled low when no components are asserting binary values on the data wire.

28. A master component that is configured to do the following when coupled to a slave component via a clock wire and a data wire:

an act of determining that an operation is to be performed on the slave component;

an act of monitoring the data wire of the two-wire interface upon determining that the operation is to be performed on the slave component;

an act of detecting at least the predetermined number of consecutive bits of the same binary polarity have occurred on the data wire during the act of monitoring the data wire; and

an act of asserting a frame of a two-wire interface on the data wire in response to the act of detecting that the predetermined number of consecutive bits of the same polarity have occurred on the data wire.

29. A master component in accordance with claim 28, wherein the two-wire interface is a guaranteed header two-wire interface.

30. A master component in accordance with claim 28, wherein the two-wire interface is not a guaranteed header two-wire interface.

31. A master component in accordance with claim 28, wherein the master component is implemented in a laser transmitter/receiver.

32. A master component in accordance with claim 31, wherein the laser transmitter/receiver is a 1G laser transceiver.

33. A master component in accordance with claim 31, wherein the laser transmitter/receiver is a 2G laser transceiver.

34. A master component in accordance with claim 31, wherein the laser transmitter/receiver is a 4G laser transceiver.

35. A master component in accordance with claim 31, wherein the laser transmitter/receiver is a 10G laser transceiver.

36. A master component in accordance with claim 31, wherein the laser transmitter/receiver is a laser transceiver suitable for fiber channels greater than 10G.

37. A master component in accordance with claim 31, wherein the laser transmitter/receiver is an XFP laser transceiver.

38. A master component in accordance with claim 31, wherein the laser transmitter/receiver is an SFP laser transceiver.

39. A master component in accordance with claim 31, wherein the laser transmitter/receiver is a SFF laser transceiver.