Time signal receiver and decoder

• US 20050129156A1
• Filed: 12/15/2003
• Published: 06/16/2005
• Est. Priority Date: 12/15/2003
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Lourens, Ruan, Eagar, Layton W., Cooper, Russell Eugene
• Granted Patent: US 7,324,615 B2
• Time in Patent Office: Days
• US Class Current: 375/350
• CPC Class Codes: G04R 20/10 Tuning or receiving; Circuits therefor
• CPC Class Codes: H03H 11/1252 Two integrator-loop-filters
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H04B 1/24 the receiver comprising at least one semiconductor device having three or more electrodes

Abstract

A time signal receiver and decoder receives, detects and stores time information from time signals, e.g., WWV, WWVH, WWVB (USA), JJY (Japan), MSF (UK) and the like. The time information may be used for a self setting clock, and the clock may be used as a reference in time sensitive applications, devices and systems. The time signal receiver may use a high-Q state variable bandpass filter or an anti-notch filter circuit for selectivity at the time signal frequency of interest. The decoder is coupled to the time signal receiver, decodes the time information in the received time signal and may store the decoded time information.

Claims

1. An apparatus for receiving and decoding a radio frequency time signal, comprising:

a time signal receiver tuned to a frequency of and amplifying a time signal;

a demodulator coupled to the time signal receiver, wherein the demodulator demodulates the amplified time signal;

a decoder coupled to the demodulator, wherein the decoder decodes the demodulated time signal; and

wherein the time signal receiver, demodulator and decoder are fabricated on a integrated circuit die.

2. The apparatus of claim 1, wherein the time signal receiver is coupled to an antenna for reception of the time signal.

3. The apparatus of claim 1, wherein the time signal receiver is a tuned radio frequency receiver having an anti-notch filter circuit.

4. The apparatus of claim 3, wherein the tuned radio frequency receiver has an amplifier with an inverting input, a non-inverting input and an output, and the anti-notch circuit is a bridge circuit.

5. The apparatus of claim 4, wherein the bridge circuit is in a feedback path coupled to the amplifier output.

6. The apparatus of claim 4, wherein the bridge circuit is in a feedback path coupled to the amplifier inverting input.

7. The apparatus of claim 4, wherein the bridge circuit is in a signal path coupled to the amplifier inverting input.

8. The apparatus of claim 3, wherein adjustments of quality (Q) and center frequency of the anti-notch filter circuit are substantially independent.

9. The apparatus of claim 3, wherein the anti-notch filter circuit is a bandpass filter circuit having high quality (Q).

10. The apparatus of claim 1, wherein the amplifier is an operational amplifier.

11. The apparatus of claim 1, further comprising a time register for storing time information from the demodulated and decoded time signal.

12. The apparatus of claim 1, further comprising packaging the integrated circuit die in an integrated circuit package.

13. The apparatus of claim 12, wherein the integrated circuit package is selected from the group consisting of PDIP, SOIC, MSOP, TSSOP, and QSOP.

14. A method for receiving and decoding a radio frequency time signal, said method comprising the steps of:

tuning a time signal receiver tuned to a time signal;

amplifying the time signal with the time signal receiver;

demodulating the amplified time signal; and

decoding the demodulated time signal;

wherein the time signal receiver is a tuned radio frequency receiver having an anti-notch filter circuit.

15. The method of claim 14, further comprising the step of storing time information from the decoded time signal.

16. The method of claim 14, wherein the tuned radio frequency receiver has an amplifier with an inverting input, a non-inverting input and an output, and the anti-notch circuit is a bridge circuit.

17. The method of claim 16, wherein the bridge circuit is in a feedback path coupled to the amplifier output.

18. The method of claim 16, wherein the bridge circuit is in a feedback path coupled to the amplifier inverting input.

19. The method of claim 16, wherein the bridge circuit is in a signal path coupled to the amplifier inverting input.

20. The method of claim 16, wherein the steps of adjusting quality (Q) and center frequency of the anti-notch filter circuit are substantially independent.

21. A system for receiving and decoding a radio frequency time signal, said system comprising:

an antenna for receiving a radio frequency time signal;

a variable gain amplifier coupled to said antenna;

a state variable bandpass filter coupled to said variable gain amplifier, where said state variable bandpass filter is tuned to the radio frequency time signal carrier frequency;

a time signal detector for demodulating time information from the radio frequency time signal, said time signal detector coupled to said state variable bandpass filter; and

a digital processor coupled to and controlling said variable gain amplifier and said state variable bandpass filter, said digital processor receiving the demodulated time information from said time signal detector,

wherein said variable gain amplifier, said state variable bandpass filter, said time signal detector and said digital processor are fabricated on a integrated circuit die.

22. The system of claim 21, wherein said antenna is parallel resonant at the radio frequency time signal carrier frequency.

23. The system of claim 21, further comprising a high level signal strength logic circuit and a low level signal strength logic circuit for determining when reception of the radio frequency time signal is less than a low signal level and above a high signal level.

24. The system of claim 23, wherein:

the high level signal strength logic circuit is at a first logic level when the radio frequency time signal is less than or equal to the high signal level and is at a second logic level when the radio frequency time signal is greater than the high signal level; and

the low level signal strength logic circuit is at a first logic level when the radio frequency time signal is less than or equal to the low signal level and is at a second logic level when the radio frequency time signal is greater than the low signal level.

25. The system of claim 24, wherein the high level signal strength logic circuit and the low level signal strength logic circuit are used in controlling how much said variable gain amplifier amplifies the radio frequency time signal coupled to said state variable bandpass filter.

26. The system of claim 21, further comprising an antenna tuner coupled between said antenna and said variable gain amplifier, wherein said antenna tuner is controlled by said digital processor.

27. The system of claim 21, wherein the digital processor is selected from the group consisting of microcontroller, microprocessor, programmable logic array (PLA), application specific integrated circuit (ASIC) and digital signal processor (DSP).

28. The system of claim 21, wherein said digital processor controls tuning of said state variable bandpass filter to the carrier frequency of the radio frequency time signal.

29. The system of claim 28, wherein the digital processor auto-correlates the demodulated time information with a know time information format for tuning said state variable bandpass filter.

30. The system of claim 29, wherein the auto-correlation of the demodulated time information is performed by digitally cross-correlating the demodulated time information and the known time information.

31. The system of claim 21, wherein the digital processor controls said state variable bandpass filter bandwidth (Q).

32. The system of claim 21, wherein said state variable bandpass filter may be tuned from about 38 kHz to about 77 kHz.