Surface treatment for multi-layer wafers formed from layers of materials chosen from among semiconducting materials

• US 20050130429A1
• Filed: 08/10/2004
• Published: 06/16/2005
• Est. Priority Date: 12/10/2003
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation), Soitec Silicon On Insulator Technologies SA (Soitec S.A.)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation), Soitec S.A.
• Inventors: Lagahe-Blanchard, Christelle, Moriceau, Hubert, Rayssac, Olivier, Fournel, Franck, Blondeau, Beryl
• Granted Patent: US 6,991,944 B2
• Time in Patent Office: Days
• US Class Current: 438/690
• CPC Class Codes: H01L 21/02032 by reclaiming or re-processing
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: Y10S 438/974 Substrate surface preparation

Abstract

This invention relates to a process for treatment of a multi-layer wafer with materials having differential thermal characteristics, the process comprising a high temperature heat treatment step that can generate secondary defects, characterised in that this process includes a wafer surface preparation step before the high temperature heat treatment step.

Claims

1. In a process for treatment of a multi-layer wafer made of materials having differential thermal characteristics wherein the process comprises a high temperature heat treatment that can generate secondary defects in working surfaces of the wafer, the improvement which comprises preparing the working surface(s) of the wafer prior to the high temperature treatment to reduce or eliminate such secondary defects.

2. The process of claim 1, wherein the wafer includes at least two layers that behave or respond differently to the high temperature heat treatment.

3. The process of claim 1, wherein the working surface(s) of the wafer is prepared by thinning the wafer surface layer.

4. The process of claim 1, wherein the working surface(s) of the wafer is prepared by polishing.

5. The process of claim 1, wherein the polishing is mechanical-chemical polishing.

6. The process of claim 1, wherein the working surface(s) is subject to ionic or chemical etching.

7. The process of claim 1, wherein the differential thermal characteristics include a combination of the following conditions:

at least some layers of the wafer are associated with different thermal expansion coefficients, and

there is a layer with a significant thickness close to the surface layer of the wafer associated with a coefficient of thermal expansion that is significantly different from the coefficient of thermal expansion associated with the surface layer.

8. The process of claim 1, wherein the wafer comprises a silicon support substrate and a surface layer made of Ge or SiGe.

9. The process of claim 1, wherein the high temperature heat treatment comprises rapid thermal annealing.

10. The process of claim 1, wherein the high temperature heat treatment comprises smoothing annealing.

11. The process of claim 1, which further comprises a second treatment in association with the preparing step designed to prevent the appearance of defect lines during the high temperature heat treatment.

12. The process of claim 11, wherein the second treatment includes a second heat treatment.

13. The process of claim 11, wherein the second heat treatment is conducted prior to the preparing step.

14. The process of claim 11, wherein the second heat treatment is carried out with a thermal budget lower than a limiting thermal budget beyond which defects will appear during the high temperature heat treatment.

15. The process of claim 14, wherein the wafer is an silicon on quartz wafer and the second heat treatment is carried out with a thermal budget less than or equal to the thermal budget corresponding to two hours of annealing at a temperature of 700°

C.

16. The process of claim 14, wherein the wafer is a germanium on silicon wafer and the second heat treatment is carried out with a thermal budget less than or equal to the thermal budget corresponding to two hours of annealing at a temperature of 500°

C.

17. The process of claim 11, wherein the second treatment includes a second chemical treatment.

18. The process of claim 17, wherein the second chemical treatment is carried out after the preparation step.

19. The process of claim 17, wherein the second chemical treatment comprises wet or dry etching.

20. The process of claim 17, wherein the second chemical treatment comprises deposition of an oxide on the working surface followed by selective etching of the oxide so as to define an etching pattern.

21. The process of claim 17, wherein the second chemical treatment uses overlapping back face etching.

22. The process of claim 11, wherein the second treatment includes a second mechanical treatment.

23. The process of claim 22, wherein the second mechanical treatment is carried out after the preparation step.

24. The process of claim 22, wherein the second mechanical treatment includes diamond cutting or laser or ionic bombardment of neutral molecules.

25. The process of claim 22, wherein the second mechanical treatment uses local polishing at the ring, to make a bevel.

26. The process of claim 25, wherein the second treatment includes the definition of regions to be isolated from any singular points in the surface layer of the wafer.

27. The process of claim 26, wherein the second treatment uses a photolithography that etches grooves delimiting the isolated regions in the surface of the said surface layer.

28. The process of claim 27, wherein the isolated regions correspond to required locations at which chips will be formed on the wafer.

29. The process of claim 28, wherein the isolated regions are defined such that their contour does not form a point defect.