Variable-gain low noise amplifier for digital terrestrial applications

• US 20050130617A1
• Filed: 01/10/2005
• Published: 06/16/2005
• Est. Priority Date: 12/02/2002
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Brooks, Charles, Burns, Lawrence M., Dauphinee, Leonard
• Granted Patent: US 7,260,377 B2
• Time in Patent Office: Days
• US Class Current: 455/253.200
• CPC Class Codes: G01R 31/2607 Circuits therefor G01R31/2642 takes precedence
• CPC Class Codes: G01R 31/30 Marginal testing, e.g. by varying supply voltage testing computers during standby operation or idle time G06F11/22
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H04B 1/109 by improving strong signal performance of the receiver when strong unwanted signals are present at the receiver input
• CPC Class Codes: H04B 1/18 Input circuits, e.g. for coupling to an antenna or a transmission line coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H
• CPC Class Codes: H04N 5/4446 IF amplifier circuits specially adapted for B&W TV RF amplifiers in general H03F3/189
• CPC Class Codes: H04N 5/52 Automatic gain control
• CPC Class Codes: H04N 7/102 Circuits therefor, e.g. noise reducers, equalisers, amplifiers H04N7/108 takes precedence

Abstract

A multi-stage amplifier assembly configured to receive a terrestrial digital television (“DTV”) input signal including multiple frequency channels. The amplifier assembly optionally includes a PIN diode coupled across differential inputs to a first stage of the multi-stage amplifier assembly. The PIN diode is controlled to attenuate the input when an exceptionally large signal is present in a channel adjacent to a desired channel. The PIN diode, essentially a variable resistor, permits the multi-stage amplifier assembly to maintain dynamic range in such situations for reasonable tradeoffs. The amplifier assembly further optionally includes an out-of-band second stage LNA. The amplifier assembly further optionally includes a multi-band input filter. The multi-band filer insures that the AGC operates on the TV band of interest, thus improving the linearity of the system. The invention can be implemented in CMOS and/or SiGe.

Claims

1. An amplifier assembly comprising:

a first stage amplifier configured to amplify a digital input signal, to thereby produce at an output of the first stage amplifier an amplified first signal with multiple frequency channels; and

a second stage amplifier receiving to an output of the first stage amplifier, the second stage amplifier configured to amplify the amplified first signal, to thereby produce at its respective output a respective second amplified signal including the multiple frequency channels.

2. The amplifier assembly of claim 1, wherein the first stage amplifier includes a first stage Variable Gain Amplifier (VGA) with a gain controlled in response to one or more gain control signals.

3. The amplifier assembly of claim 1, farther comprising an Automatic Gain Control (AGC) module configured to generate the one or more gain control signals in response to a power of the first amplified signal.

4. The amplifier assembly of claim 3, wherein the VGA includes a plurality of variable gain stages arranged in parallel with one another, each of the gain stages having a gain controlled responsive to a corresponding one of the one or more gain control signals.

5. The amplifier assembly of claim 3, wherein the AGC module is configured to generate the one or more AGC control signals according to a ramp function, and thereby change the gain of the first stage VGA according to the ramp function.

6. The amplifier assembly of claim 5, wherein the gain change of the first stage VGA is smooth and continuous responsive to the ramp function.

7. The amplifier assembly of claim 3, wherein an input of the AGC module is coupled to an output the second stage amplifier.

8. The amplifier assembly of claim 1, wherein the second stage amplifier comprises a second stage VGA.

9. The amplifier assembly of claim 8, wherein the second stage comprises a plurality of second stage VGAs, wherein:

each of a first sub-plurality of the second stage Variable Gain Amplifiers (VGAs) has a first gain; and

each of a second sub-plurality of the second stage VGAs has a second gain that is less than the programmed first gain.

10. The amplifier assembly of claim 9, wherein a ratio of the first gain to the second gain is in a range of 1:

1 to 2;

1.

11. The amplifier assembly of claim 1, wherein the second stage comprises a plurality of second stage amplifiers, including an out-of-band second stage amplifier.

12. The amplifier assembly of claim 1, wherein the input signal is at least one of an NTSC TV signal, a PAL TV signal, a SECAM TV signal, a digital data signal, and a digital TV signal.

13. The amplifier assembly of claim 1, wherein the first stage amplifier is a differential amplifier.

14. The amplifier assembly of claim 1, wherein the second stage amplifier is a differential amplifier.

15. The amplifier assembly of claim 1, wherein the first stage amplifier includes a plurality of parallel gain stages having their respective outputs combined together at the first stage amplifier output.

16. The amplifier assembly of claim 1, wherein the first stage amplifier comprises:

an input node;

a first plurality of amplifiers having their inputs coupled to the input node;

an attenuation ladder coupled to the input node; and

a second plurality of amplifiers having their respective inputs coupled to successive corresponding taps of the attenuation ladder,

wherein the outputs of the first plurality of amplifiers and the outputs of the second plurality of amplifiers are combined together at the output of the first stage amplifier.

17. The amplifier assembly of claim 16, further comprising:

an integrated circuit (IC) substrate, the first stage amplifier being constructed on the IC substrate; and

an input resistor external to the IC substrate and coupled to the input node, wherein the input resistor and the attenuation ladder together set an input impedance of the amplifier assembly.

18. The amplifier assembly of claim 1, further comprising:

a control interface coupled to the first stage amplifier and to each of the second stage amplifiers, the control interface being configured to perform at least one of the following;

set the gain of the first stage amplifier;

access the gain of the first stage amplifier; and

set the gain of each of the second stage amplifiers.

19. The amplifier assembly of claim 1, further comprising:

an integrated circuit (IC) substrate, the first stage amplifier and the plurality of second stage amplifiers being constructed on the IC substrate; and

process sense circuits constructed on the IC substrate, each of the process sense circuits producing a respective sensed signal indicative of a process-based parameter of the IC substrate, wherein the process-based parameter is one of;

a transconductance of the IC substrate;

a resistivity per unit area of the IC substrate; and

a gate-to-source threshold voltage for transistors constructed on the IC substrate.

20. An amplifier assembly;

a substrate;

a first stage Variable Gain Amplifier (VGA) configured to have a gain controlled in response to one or more gain control signals;

a second stage Variable Gain Amplifier (VGA) having an input coupled to an output of the VGA;

an (Automatic Gain Control) AGC module configured to generate the one or more control signals responsive to a power of an amplified signal produced by the first stage VGA; and

a control interface coupled to the first stage VGA, the second stage VGA, and the AGC module,

wherein the first stage VGA, the second stage VGA, the control interface, and at least a portion of the AGC module are all on the substrate.

21. The amplifier assembly of claim 20, further comprising a process monitor, on the substrate for monitoring process-based parameters of the substrate.

22. The amplifier assembly of claim 21, wherein the control interface is coupled to the processor monitor.

23. The system of claim 20, wherein the AGC module maintains an amplitude of each of the amplified signals at a respective constant level relative to a varying amplitude of the input signal.

24. The system of claim 23, wherein the AGC module is configured to operate autonomously.

25. The system of claim 20, further comprising a PIN diode coupled between differential input terminals of the first stage amplifier.

26. The system of claim 25, further comprising a current-driver/operational amplifier coupled to the PIN diode and configured to drive the PIN diode.

27. The system of claim 20, further comprising a multi-band input filter coupled to an input of the first stage amplifier.

28. The system of claim 27, wherein the multi-band input filter comprises a triple-band input filter.

29. The system of claim 28, wherein the triple-band input filter comprises:

a low-VHF band-pass filter;

a hi-VHF band-pass filter; and

a UHF band-pass filter.

30. The system of claim 29, wherein the low-VHF band-pass filter passes a band in a range of approximately 54-99 MHz, the hi-VHF band-pass filter passes a band in a range of approximately 174-216 MHz, and the UHF band-pass filter passes a band in a range of approximately 470-890 MHz.

31. The system of claim 27, wherein the first stage amplifier comprises a plurality of first stage amplifiers, each coupled to a corresponding input filter.