Performance monitoring based dynamic voltage and frequency scaling

• US 20050132238A1
• Filed: 12/16/2003
• Published: 06/16/2005
• Est. Priority Date: 12/16/2003
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Nanja, Murthi
• Granted Patent: US 7,770,034 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Voltage and frequency scaling techniques that are based upon monitored data are provided. The techniques may be used to better manage the power and energy consumption of a processor in an embedded system, such as a cellular telephone, personal data assistant, smart device, or the like. The techniques may be used with processors that offer a performance monitoring capability. The performance monitor may monitor thread-level utilization at runtime. Instructions per cycle and memory references per cycle are example metrics that may be monitored by the performance monitor. The voltage and frequency scaling techniques may adjust the operating voltage and operating frequency of the processor based on the values of these two metrics. For example, the techniques may include accessing a voltage and frequency scheduler lookup table. The techniques may be employed with non-embedded systems, as well, embedded systems.

Claims

1. An article comprising a machine-accessible medium having stored thereon instructions that, when executed by a machine, cause the machine to:

obtain from a performance monitor runtime performance data indicative of a thread-level utilization; and

based on the performance data, adjust an operating voltage or an operating frequency of the machine.

2. The article of claim 1, wherein the performance monitor is a Performance Monitoring Unit (PMU).

3. The article of claim 2, wherein the PMU is part of a central processing unit (CPU) within the machine.

4. The article of claim 2, wherein the PMU includes a plurality of counters for measuring different performance data.

5. The article of claim 1, wherein the runtime performance data is selected from the group consisting of instruction cache misses, data cache misses, instructions executed, branches executed, branch mis-predicts, instruction translation look-up buffer TLB misses, data translation look-up buffer TLB misses, stalls due to data dependency, and data cache write-backs.

6. The article of claim 1, having further instructions that, when executed by the machine, cause the machine to:

in response to the performance data, determine if the operating voltage and operating frequency should be adjusted upward or scaled down.

7. The article of claim 6, having further instructions that, when executed by the machine, cause the machine to:

compare the performance data to a voltage and frequency scheduler lookup table that stores at least one voltage value and at least one frequency value.

8. The article of claim 1, having further instructions that, when executed by the machine, cause the machine to:

obtain a plurality of runtime performance data; and

in response to the plurality of runtime performance data, adjusting the operating voltage and the operating frequency.

9. The article of claim 1, wherein the performance data is an instructions-per-cycle metric.

10. The article of claim 1, wherein the performance data is a memory references-per-cycle metric.

11. The article of claim 1, having further instructions that, when executed by the machine, cause the machine to:

operate the performance monitor in an operating system environment in communication with a platform hardware environment, in a kernel mode, and in communication with an end user code, in a user mode.

12. The article of claim 1, wherein the instructions, when executed by the machine, cause the machine to adjust the operating voltage and the operating frequency.

13. A method comprising:

obtaining, from a performance monitor, runtime performance data indicative of a thread-level utilization for a central processing unit (CPU) having an operating voltage and an operating frequency;

in response to the runtime performance data, determining if either the operating voltage or the operating frequency is at a desired value; and

in response to the determination, adjusting the operating voltage or the operating frequency.

14. The method of claim 13, further comprising:

adjusting both the operating voltage and the operating frequency.

15. The method of claim 14, further comprising adjusting the operating voltage and the operating frequency upward.

16. The method of claim 14, further comprising adjusting the operating voltage and the operating frequency downward.

17. The method of claim 13, wherein the performance monitor is a Performance Monitoring Unit (PMU).

18. The method of claim 13, wherein the runtime performance data is selected from the group consisting of instruction cache misses, data cache misses, instructions executed, branches executed, branch mis-predicts, instruction translation look-up buffer misses, data translation look-up buffer misses, stalls due to data dependency, and data cache write-backs.

19. The method of claim 13, further comprising comparing the performance data to a voltage and frequency scheduler lookup table that includes at least one voltage value and at least one frequency value.

20. The method of claim 19, further comprising:

benchmarking the CPU;

determining the at least one voltage value and the at least one frequency value in response to the benchmarking; and

creating a lookup table of the at least one voltage value and the at least one frequency value.

21. The method of claim 13, further comprising adjusting the operating voltage or the operating frequency in response to an instructions-per-cycle metric or a memory-references-per-cycle metric.