Characterization and reduction of variation for integrated circuits

• US 20050132306A1
• Filed: 12/06/2004
• Published: 06/16/2005
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Praesagus Inc.
• Inventors: White, David, Smith, Taber H., Mehrotra, Vikas
• Granted Patent: US 7,383,521 B2
• Time in Patent Office: Days
• US Class Current: 716/114
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Claims

1. A method comprising

based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, generating a strategy for sizing and placement of buffers or repeaters in interconnect wires, and

using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the buffers or repeaters to be placed,

the use of the model and the electrical impact analysis being embedded as part of the generation of the buffer or repeater placement strategy.

2. A method comprising

based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, determining the number of buffers or repeaters in interconnect wires, and

using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the buffers or repeaters to be placed,

the use of the model and the electrical impact analysis being embedded as part of the generation of the buffer or repeater placement strategy.

23. The method of claims 2, 3, and 5 as feedback to the place and route process

3. A method comprising

based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, predicting or simulating propagation delays for single or multiple interconnect levels.

4. The method claim 3 using the model and the electrical impact analysis being embedded as part of the generation of strategies to reduce propagation delays.

5. The method claim 3 using the model and the electrical impact analysis as part of the design verification process.

6. A method comprising

based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, predicting or simulating power consumption for single or multiple interconnect levels.

7. The method claim 6 also including the model and the electrical impact analysis being embedded as part of the generation of strategies to reduce power consumption.

8. The method claim 6 also including using the model and the electrical impact analysis as part of a design verification process.

9. The method claim 6 also including using the model and the electrical impact analysis as part of a power and timing analysis process.

10. The method claim 6 also including using the model and the electrical impact analysis with power, signal integrity, and timing analysis tools.

11. The method claim 6 also including using the model and the electrical impact analysis with a design rule checker (DRC) or layout verification schematic (LVS) tools.

12. The method claim 6 also including using the model and the electrical impact analysis with resistance and capacitance extraction tools.

13. The method of claim 6 in which the process flow includes CMP.

14. The method of claim 6 in which the process flow includes plasma etch, lithography or deposition process steps.

15. A method comprising

based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, predicting feature dimension variations for a single level of interconnect geometries.

16. The method of claim 15 in which the feature dimension variations are associated with at least one of printed feature widths, etch trench width, etch trench depth, etched sidewall angle, dishing, erosion, or total copper loss.

17. A method comprising

based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, generating a strategy for placement of dummy fill in the process, and

using the pattern dependent model and the electrical impact analysis to evaluate the expected impact of the placed dummy fill on buffer sizing and placement,

the use of the model and the electrical impact analysis being embedded as part of the generation of the buffer sizing and placement strategy.

18. A method comprising

using a pattern-dependent model to predict variations that will occur in an integrated circuit as a result of processing up to a predetermined interconnect level, and

sizing and placing buffers within interconnect feature to accommodate the variations.

19. The method of claim 18 in which at least one of the predicting and the adjusting is provided as a service in a network.

20. The method of claim 19 in which the network comprises an intranet, an extranet, or an internet, and the predicting or adjusting is provided in response to user requests.

21. A method comprising

based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, determining the placement of integrated circuit components

22. A method comprising

based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, determining the routing of integrated circuit wires.

24. The method comprising

based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, determining

using the pattern dependent model and the electrical impact analysis to compare results.

25. The method of claim 24 where the results are displayed in the form of full or partial chip images.

26. The method of claim 24 where the results are displayed in the form of statistical histograms.

27. The method of claim 25 where the images contain thickness, total copper loss, sheet resistance, dishing and erosion information.

28. The method of claim 26 where the histograms contain thickness, total copper loss, sheet resistance, dishing and erosion information.

29. The method of claim 24 where the comparison is between two or more different designs.

30. The method of claim 24 where the comparison is between two or more process recipe or tool settings for the same design.

31. The method of claim 24 where the comparison is between two different process steps for the same design.

32. The method of claim 24, 25, 26, 27, 28 or 29 where the results are shown through a web browser or communicated across an internet, intranet and extranet network connection.

33. The method of claim 24, 25, 26, 27, 28 or 29 where the results are used to select a design for fabrication.

34. A method comprising

using a pattern dependent model to determine manufacturing recipe and equipment settings for a process used to fabricate an integrated circuit (IC), the manufacturing recipe and equipment settings reducing process-induced variation in wafer state parameters or electrical performance.

35. The method of claim 34 in which the wafer state parameters compriseat least one of film thickness across the full fabricated IC.

36. The method of claim 34 also including using test wafers to characterize pattern dependencies in at least a portion of the integrated circuit fabrication process and using the pattern dependencies in the model.

37. The method of claim 36 in which the portion of the fabrication process comprises electroplating.

38. The method of claim 36 in which the portion of the fabrication process comprises oxide deposition.

39. The method of claim 36 in which the portion of the fabrication process comprises chemical mechanical polishing (CMP).

40. The method of claim 36 in which the portion of the fabrication process comprises plasma etch.

41. The method of claim 36 in which the portion of the fabrication process comprises a lithography process.

42. The method of claim 34, 35, 36, 37, 38, 39, 40 or 41 in which the model maps pattern dependent features to the process induced variation in wafer state parameters.

43. The method of claim 42 in which the wafer state parameters include at least one of film thickness, array height, step height, sheet resistance, capacitance, crosstalk noise, and coupling capacitance.

44. The method of claim 42 in which the pattern dependent features include at least one of linespace, linewidth, and effective density.

45. The method of claim 34 also including using the model to generate full-chip predictions of variation in wafer state and electrical parameters.

46. The method of claim 34 or 45 also including using a cost-function to measure results of the predictions.

47. The method of claim 46 also including using the cost function to compare one set of recipe or equipment settings to another.

48. The method of claim 46 also including using optimization methods to select recipe and equipment settings that minimize variation in wafer-state or electrical parameters.

49. The method of claim 48 in which the optimization methods include at least one of simplex, conjugate gradient, simulated annealing, dynamic programming, approximate dynamic programming, linear programming, and approximate linear programming.

50. The method of claim 49 also including using quadratic cost functions to facilitate convergence of the optimization methods

51. The method of claim 34 in which the process comprises a single process step.

52. The method of claim 34 in which the process comprises more than one one process step or a process flow

53. The method of claim 34 also including communicating one or more sets of the manufacturing recipe and equipment settings to a user through a graphical user interface.

54. The method of claim 34 also including communicating at least one manufacturing recipe directly to a process tool or a fabrication automation system

55. The method of claim 34 also including communicating at least one manufacturing recipe directly to a memory device attached to a wafer carrier or prescribed to a particular wafer lot.

56. The method of claim 34 also including using the pattern dependent model to predict or simulate electrical performance or electrical parameters as a result of a single process step.

57. The method of claim 34 also including using the pattern dependent model to predict or simulate electrical performance or electrical parameters as a result of more than one process steps or a process flow

58. The method of claim 34 also including using actual product wafers to develop the model, the model mapping pattern dependent features to at least one of process-induced variation in wafer state parameters or variation in electrical parameters.

59. The method of claim 58 in which the pattern dependent features include at least one of linespace, linewidth, and effective density,

60. The method of claim 58 in which the wafer state parameters include at least one of film thickness, array height, step height,

61. The method of claim 58 in which the electrical parameters include at least one of sheet resistance, capacitance, crosstalk noise, and coupling capacitance.

62. The method of claim 58 also including certifying manufacturability of the IC device before mask tape-out and manufacturing.

63. The method of claim 34 also including simulating a final electrical performance of the IC before mask tape-out and manufacturing.

64. The method of claim 34 also including determining a process flow, among several candidates, for an IC design

65. The method of claim 34 also including varying recipe parameters to characterize pattern dependencies in an IC manufacturing process.

66. The method of claim 65 also including processing the recipe at points of a life cycle of the process to characterize process drift.

67. The method of claim 66 in which the process drift comprises CMP pad wear or build up on the walls of a plasma reactor.

68. The method of claim 34 implemented in software carried on a medium.

69. The method of claim 34 also including providing a graphical user interface to permit a user to access results.

70. The method of claim 34 used for process synthesis and implemented on a web server.

71. The method of claim 34 used for process optimization and implemented on a web server.

72. The method of claim 34 implemented on a web server.

73. The method of claim 70, 71 or 72 also including generating custom web applications for the web server with respect to different users.

74. The method of claim 34 also including identifying post-manufacture faults spatially across a die for one process step or multiple process steps in a flow.

75. The method of claim 34 also including receiving, through a web server, manufacturability predictions for the IC using a particular process or tool.

76. The method of claim 34 also including using a web server to provide automatically chosen recipe or equipment settings directly to a process tool or flow of process tools or steps.

77. The method of claim 34 also including providing an optimization to a user from a web server in response to a single click.

78. The method of claim 34 also including providing an optimization to a user from a web server in response to a single click.

79. The method of claim 34 also including characterizing process drift and shifts over a number of process hours or a number of wafers processed

80. The method of claim 34 also including scheduling maintenance and repair of process tools.

81. The method of claim 34 also including selecting consumable sets.

82. The method of claim 34 in which the consumable sets include polishing pads, polishing slurries, or gas composition.

92. The method of claim 42 also including characterizing unique aspects related to pattern dependencies of a tool for diagnostics or control.

93. The method of claim 42 also including building a database or library of results for analysis.

94. The method of claim 42 also including compiling aggregate statistics regarding tool or consumable behavior.

95. The method of claim 42 also including establishing tool or design benchmarks.

96. The method of claim 42 also including providing data across a network.

83. A method comprising

based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, generating a strategy for comparing consumable sets or equipment, and

using the pattern dependent model and the electrical impact analysis to evaluate the expected results of integrated circuit designs processed using a selected one of the consumable sets or equipment.

84. The method of claim 83 in which the consumable sets comprise slurries, pads, or gases.

85. The method of claim 83 in which the equipment comprises CMP, ECD, plasma etch, lithography or deposition equipment.

86. A method comprising

based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, generating a strategy for analysis or diagnosis of equipment or consumable set results, and

using the pattern dependent model and the electrical impact analysis to evaluate the expected results of an integrated circuit design processed using a selected one of the consumable sets or equipment.

87. The method of claim 86 in which the consumables comprise at least one of slurries, pads, or gasses.

88. The method of claim 86 in which the equipment comprises CMP, ECD, plasma etch, lithography or deposition equipment.

89. A method comprising

based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, generating a prediction of isolation trench geometries.

90. The method of claim 89 in which the process flow includes CMP.

91. The method of claim 89 in which the process flow includes plasma etch.

97. The method of claim 89 or 90 also including predicting trench rounding at an interface of an active device region and an isolation trench region.

98. The method of claim 91 also including predicting a threshold voltage at the interface of the active device region and isolation trench region.

99. The method of claim 89 also including predicting a leakage current at an interface of an active device region and an isolation trench region.

100. The method of claim 89 also including predicting polysilicon stringers at an interface of an active device region and an isolation trench region.

101. The method of claim 89 also including defining process steps or flows in the creation of shallow trench isolation structures

102. The method of claim 101 also including selecting a particular shallow trench isolation design.

103. The method of claim 89 also including selecting a design or process characteristics to influence trench corner rounding.

104. A method comprising

based on an electrical impact analysis and a pattern dependent model of a trench isolation fabrication process flow of one or more steps, generating a strategy for placement of dummy fill oxide regions in the process, and

using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the dummy fill to be placed, the use of the model and the electrical impact analysis being embedded as part of the generation of the dummy fill placement strategy.