Characterization and reduction of variation for integrated circuits
First Claim
1. A method comprising based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, generating a strategy for sizing and placement of buffers or repeaters in interconnect wires, and using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the buffers or repeaters to be placed, the use of the model and the electrical impact analysis being embedded as part of the generation of the buffer or repeater placement strategy.
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Accused Products
Abstract
A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.
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Citations
104 Claims
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1. A method comprising
based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, generating a strategy for sizing and placement of buffers or repeaters in interconnect wires, and using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the buffers or repeaters to be placed, the use of the model and the electrical impact analysis being embedded as part of the generation of the buffer or repeater placement strategy.
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2. A method comprising
based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, determining the number of buffers or repeaters in interconnect wires, and using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the buffers or repeaters to be placed, the use of the model and the electrical impact analysis being embedded as part of the generation of the buffer or repeater placement strategy.
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3. A method comprising
based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, predicting or simulating propagation delays for single or multiple interconnect levels.
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6. A method comprising
based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, predicting or simulating power consumption for single or multiple interconnect levels.
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15. A method comprising
based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, predicting feature dimension variations for a single level of interconnect geometries.
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17. A method comprising
based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, generating a strategy for placement of dummy fill in the process, and using the pattern dependent model and the electrical impact analysis to evaluate the expected impact of the placed dummy fill on buffer sizing and placement, the use of the model and the electrical impact analysis being embedded as part of the generation of the buffer sizing and placement strategy.
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18. A method comprising
using a pattern-dependent model to predict variations that will occur in an integrated circuit as a result of processing up to a predetermined interconnect level, and sizing and placing buffers within interconnect feature to accommodate the variations.
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21. A method comprising
based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, determining the placement of integrated circuit components
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22. A method comprising
based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, determining the routing of integrated circuit wires.
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24. The method comprising
based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, determining using the pattern dependent model and the electrical impact analysis to compare results.
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34. A method comprising
using a pattern dependent model to determine manufacturing recipe and equipment settings for a process used to fabricate an integrated circuit (IC), the manufacturing recipe and equipment settings reducing process-induced variation in wafer state parameters or electrical performance.
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83. A method comprising
based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, generating a strategy for comparing consumable sets or equipment, and using the pattern dependent model and the electrical impact analysis to evaluate the expected results of integrated circuit designs processed using a selected one of the consumable sets or equipment.
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86. A method comprising
based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, generating a strategy for analysis or diagnosis of equipment or consumable set results, and using the pattern dependent model and the electrical impact analysis to evaluate the expected results of an integrated circuit design processed using a selected one of the consumable sets or equipment.
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89. A method comprising
based on electrical impact analysis and a pattern dependent model of a fabrication process flow of one or more steps, generating a prediction of isolation trench geometries.
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104. A method comprising
based on an electrical impact analysis and a pattern dependent model of a trench isolation fabrication process flow of one or more steps, generating a strategy for placement of dummy fill oxide regions in the process, and using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the dummy fill to be placed, the use of the model and the electrical impact analysis being embedded as part of the generation of the dummy fill placement strategy.
Specification