Printed wiring board and semiconductor device

• US 20050133249A1
• Filed: 12/16/2004
• Published: 06/23/2005
• Est. Priority Date: 12/19/2003
• Status: Abandoned Application

• Current Assignee: Mitsui Mining and Smelting Company Limited
• Original Assignee: Mitsui Mining and Smelting Company Limited
• Inventors: Fujii, Nobuaki
• Application Number:
  US11/013,611
• Publication Number:
  US 20050133249A1
• Time in Patent Office: Days
• US Class Current: 174/250
• CPC Class Codes: H05K 1/0266 Marks, test patterns or identification means
• CPC Class Codes: H05K 1/0271 Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
• CPC Class Codes: H05K 2201/09781 Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
• CPC Class Codes: H05K 2203/0594 Insulating resist or coating with special shaped edges
• CPC Class Codes: H05K 3/3452 Solder masks

Abstract

A printed wiring board has a large number of wirings formed substantially parallel to one another, a dummy pattern is formed along the wirings and a solder resist layer is formed by coating the wirings and the dummy pattern with a solder resist. The coating thickness of said solder resist gradually decreases toward the edge, wherein the dummy pattern has a solder resist coating thickness control area. A semiconductor device includes the above-mentioned printed wiring board with an electronic part mounted thereon. Accordingly, a slope uniformly extending over the whole width of the solder resist layer is formed at the edge portion of the solder resist layer to improve electrical connectivity.

Claims

1. A printed wiring board having a large number of wirings formed substantially parallel to one another, a dummy pattern formed along the wirings and a solder resist layer formed by coating the wirings and the dummy pattern with a solder resist, the coating thickness of said solder resist being gradually decreased toward the edge, wherein:

the dummy pattern has a solder resist coating thickness control area.

2. The printed wiring board as claimed in claim 1, wherein the solder resist coating thickness control area is formed by dividing the dummy pattern into dummy fine wires and dummy spaces between the dummy fine wires, said dummy fine wires being substantially parallel to the large number of the wirings formed substantially parallel to one another.

3. The printed wiring board as claimed in claim 1, wherein the solder resist coating thickness control area is formed from a space of the dummy pattern, said space being formed by removing at least a part of an outer periphery of the dummy pattern and the interior of the dummy pattern with leaving at least a part of the outer periphery of the dummy pattern in such a manner that the original shape of the dummy pattern is recognizable.

4. The printed wiring board as claimed in claim 1, wherein the dummy pattern is any one of an alignment mark and a deformation-preventing dummy pattern.

5. A semiconductor device comprising the printed wiring board of claim 1 and an electronic part mounted on the printed wiring board.

6. A semiconductor device comprising the printed wiring board of claim 2 and an electronic part mounted on the printed wiring board.

7. A semiconductor device comprising the printed wiring board of claim 3 and an electronic part mounted on the printed wiring board.

8. A semiconductor device comprising the printed wiring board of claim 4 and an electronic part mounted on the printed wiring board.