Electromagnetic digitizer sensor array
First Claim
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1. An electromagnetic digitizer sensor coupled to a processor, comprising:
- a first array of sensing loops each coupled between the processor and a first potential node, each sensing loop in the first array being selectively connectable to the processor and further being selectively connectable to the first potential node.
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Abstract
An electromagnetic digitizer arrangement that may include a comb-like pattern of sensing traces that form various sensing loops depending upon the configurations of various switches is described. The comb arrangement of traces may be fabricated using only a single layer per sensing axis. Thus, the digitizer may be fabricated in a technology, such as indium tin oxide on glass, that cannot provide plated-through holes.
23 Citations
19 Claims
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1. An electromagnetic digitizer sensor coupled to a processor, comprising:
a first array of sensing loops each coupled between the processor and a first potential node, each sensing loop in the first array being selectively connectable to the processor and further being selectively connectable to the first potential node. - View Dependent Claims (2, 3, 4)
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5. An electromagnetic digitizer sensor coupled to a processor, comprising:
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a substrate having a first level; and
an array of sensing loops disposed completely at the first level, each of the sensing loops being selectably coupled between the processor and a potential node such that any one of the sensing loops can be selected to form a closed circuit between the processor and its respective node without being short-circuited by any of the other sensing loops. - View Dependent Claims (6, 7)
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8. An electromagnetic digitizer sensor, comprising:
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a substrate having first and second different levels;
an array of first sensing loops each disposed at the first level but not the second level; and
an array of second sensing loops each disposed at the second level but not the first level. - View Dependent Claims (9, 10)
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11. An electromagnetic digitizer sensor coupled to a processor, comprising:
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a first plurality of sensing traces electrically coupled in parallel between the processor and a first node;
a second plurality of sensing traces electrically coupled in parallel between a second node and the first node;
a first plurality of switches each coupled between one of the first plurality of sensing traces and the processor; and
a second plurality of switches each coupled between one of the second plurality of sensing paths and the second node. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification