Integrated circuit comprising a clock generator, a chip card comprising one such integrated circuit and the associated clock generation method

• US 20050133603A1
• Filed: 12/11/2002
• Published: 06/23/2005
• Est. Priority Date: 12/13/2001
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Moreaux, Christophe, Kari, Ahmed
• Granted Patent: US 7,400,874 B2
• Time in Patent Office: Days
• US Class Current: 235/492
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: H03K 5/125 Discriminating pulses measuring characteristics of individual pulses G01R29/02; separation of synchronising signals in television systems H04N5/08
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

A contactless integrated circuit receiving an RF signal comprises a clock-signal generator to produce a clock signal from a first half wave and a second half wave representing the received RF signal. Also disclosed is a method for the generation of a clock signal in which the first half wave and the second half wave are compared to produce the clock signal. The invention is adapated for use in contactless cards, transponders, and the like.

Claims

1. A contactless integrated circuit receiving an RF signal, wherein the circuit comprises a clock-signal generator to produce a clock signal by the comparison of a first half wave with a second half wave representing the received RF signal.

2. An integrated circuit according to the claim 1, wherein the clock signal is produced after a supply voltage of the integrated circuit has become available, said supply voltage, stable and continuous, being produced by a voltage generator from the first half-wave and the second half-wave.

3. An integrated circuit according to claim 1, wherein the clock circuit comprises a comparator comprising:

a first transistor and a second transistor connected in series, the supply voltage being applied to a source of the first transistor and a ground voltage (GND) being applied to the source of the second transistor, the first half wave being applied to a gate of the second transistor, the clock signal being produced at the drain of the second transistor,

a third transistor and a fourth transistor connected in series, the supply voltage being applied to a source of the third transistor and a ground voltage (GND) being applied to the source of the fourth transistor, the second half wave being applied to a gate of the fourth transistor, a gate of the first transistor being connected to the drain of the fourth transistor and a gate of the third transistor being connected to the drain of the second transistor.

8. A contactless smart card, comprising an integrated circuit according to one of the claims 1 to 7.

9. A contactless smart card, wherein the smart card includes an integrated circuit according to claim 2.

10. A contactless smart card, wherein the smart card includes an integrated circuit according to claim 3.

14. An integrated circuit according to claim 2, wherein the clock circuit comprises a comparator comprising:

a first transistor and a second transistor connected in series, the supply voltage being applied to a source of the first transistor and a ground voltage being applied to the source of the second transistor the first half wave being applied to a gate of the second transistor, the clock signal being produced at the drain of the second transistor,

a third transistor and a fourth transistor connected in series, the supply voltage being applied to a source of the third transistor and a ground voltage being applied to the source of the fourth transistor, the second half wave being applied to a gate of the fourth transistor, a gate of the first transistor being connected to the drain of the fourth transistor and a gate of the third transistor being connected to the drain of the second transistor.

4. An integrated circuit according to claim 4, comprising also:

a fifth transistor series-connected between the first transistor and the second transistor, a source and a drain of the fifth transistor being connected respectively to a drain of the first transistor and to the drain of the second transistor, and

a sixth transistor series-connected between the third transistor and the fourth transistor, a source and a drain of the sixth transistor being connected respectively to a drain of the third transistor and to the drain of the fourth transistor, an enabling signal being applied to a gate of the fifth transistor and to a gate of the sixth transistor (T66) connected together.

5. An integrated circuit according to claim 4, also comprising:

a seventh transistor comprising a drain and a source respectively connected to the drain and to the source of the second transistor, the enabling signal being applied to a gate of the of the seventh transistor (T67).

6. An integrated circuit according to claim 4, also comprising:

an eighth transistor comprising a drain and a source respectively connected to the drain and to the source of the fourth transistor, the enabling signal being applied to a gate of the eighth transistor.

11. A contactless smart card, wherein the smart card includes an integrated circuit according to claim 4.

12. A contactless smart card, wherein the smart card includes an integrated circuit according to claim 5.

13. A contactless smart card, wherein the smart card includes an integrated circuit according to claim 6.

15. An integrated circuit according to claim 5, also comprising:

an eighth transistor comprising a drain and a source respectively connected to the drain and to the source of the fourth transistor, the enabling signal being applied to a gate of the eighth transistor.

7. A method for the production of a clock signal in a contactless integrated circuit wherein, during the method, a comparison is made between a first half wave and a second half wave representing an RF signal received by the integrated circuit, the clock signal being the result of the comparison.