Semiconductor integrated circuit, semiconductor device, and manufacturing method of the semiconductor integrated circuit

• US 20050133790A1
• Filed: 12/17/2004
• Published: 06/23/2005
• Est. Priority Date: 12/19/2003
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi
• Granted Patent: US 7,436,032 B2
• Time in Patent Office: Days
• US Class Current: 257/66
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 21/76894 using a laser, e.g. laser cutting, laser direct writing, laser repair
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/38 Doping programmed, e.g. mask ROM
• CPC Class Codes: H10B 20/65 of memory structures of the ROM only type

Abstract

A chip with increased impact resistance, attractive design and reduced cost, and a manufacturing method thereof are provided. A semiconductor integrated circuit is formed on a large glass substrate, and a part of data of a ROM included therein is determined by an ink jet method or a laser cutting method. Accordingly, the cost can be reduced without requiring a photomask, resulting in an inexpensive ID chip. Further, depending on the application, the semiconductor integrated circuit is transposed to a flexible substrate, thereby an ID chip with improved impact resistance and more attractive design can be achieved.

Claims

1. A semiconductor integrated circuit comprising:

an insulating substrate; and

a read only memory over the insulating substrate,

wherein the read only memory includes a memory cell connected to a wiring formed by a droplet discharging method.

2. A circuit according to claim 1, wherein the wiring comprises at least one of gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), nickel (Ni), tantalum (Ta), bismuth (Bi), lead (Pb), indium (In), tin (Sn), zinc (Zn), titanium (Ti), aluminum (Al), and an alloy of them.

3. A circuit according to claim 1, wherein the insulating substrate is one of a glass substrate and a flexible substrate.

4. A semiconductor device comprising a semiconductor integrated circuit according to claim 1, further comprising a connecting terminal.

5. A card comprising a semiconductor device according to claim 4.

6. A tag comprising a semiconductor device according to claim 4.

7. A semiconductor device comprising a semiconductor integrated circuit according to claim 4, further comprising an antenna that is connected to the connecting terminal and formed on the semiconductor integrated circuit.

8. A device according to claim 7, wherein the antenna comprises at least one of gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), nickel (Ni), tantalum (Ta), bismuth (Bi), lead (Pb), indium (In), tin (Sn), zinc (Zn), titanium (Ti), aluminum (Al), and an alloy of them.

9. A card comprising a semiconductor device according to claim 7.

10. A tag comprising a semiconductor device according to claim 7.

11. A semiconductor integrated circuit comprising:

an insulating substrate;

a first read only memory that includes a memory cell connected to a wiring formed by a photomask; and

a second read only memory that includes a memory cell connected to a wiring formed by a droplet discharging method,

wherein the first read only memory and the second read only memory are formed on the insulating substrate.

12. A circuit according to claim 11, wherein the wiring formed by the droplet discharging method comprises at least one of gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), nickel (Ni), tantalum (Ta), bismuth (Bi), lead (Pb), indium (In), tin (Sn), zinc (Zn), titanium (Ti), aluminum (Al), and an alloy of them.

13. A circuit according to claim 11, wherein the insulating substrate is one of a glass substrate and a flexible substrate.

14. A semiconductor integrated circuit comprising:

an insulating substrate; and

a memory cell formed over the insulating substrate and connected to a wiring including a cut portion.

15. A circuit according to claim 14, wherein the insulating substrate is one of a glass substrate and a flexible substrate.

16. A semiconductor device comprising a semiconductor integrated circuit according to claim 14 further comprising a connecting terminal.

17. A card comprising a semiconductor device according to claim 16.

18. A tag comprising a semiconductor device according to claim 16.

19. A semiconductor device comprising a semiconductor integrated circuit according to claim 14 further comprising an antenna that is connected to the connecting terminal and formed on the semiconductor integrated circuit.

20. A device according to claim 19, wherein the antenna includes gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), nickel (Ni), tantalum (Ta), bismuth (Bi), lead (Pb), indium (In), tin (Sn), zinc (Zn), titanium (Ti), or aluminum (Al), or an alloy of them.

21. A card comprising a semiconductor device according to claim 19.

22. A tag comprising a semiconductor device according to claim 19.

23. A semiconductor integrated circuit comprising:

a first read only memory that includes a memory cell connected to a wiring formed by a photomask; and

a second read only memory connected to a wiring including a cut portion,

wherein the first read only memory and the second read only memory are formed on an insulating substrate.

24. A circuit according to claim 23, wherein the insulating substrate is one of a glass substrate and a flexible substrate.

25. A semiconductor integrated circuit comprising:

an insulating substrate; and

a read only memory over the insulating substrate including a memory cell connected to a wiring,

wherein the wiring comprise aggregate of grains formed by a plurality of metal particles.

26. A circuit according to claim 25, wherein the metal particles comprise at least one material selected from the group consisting of gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), nickel (Ni), tantalum (Ta), bismuth (Bi), lead (Pb), indium (In), tin (Sn), zinc (Zn), titanium (Ti), aluminum (Al), and an alloy of them.

27. A method of manufacturing a semiconductor integrated circuit, comprising the steps of:

forming on an insulating substrate a thin film transistor;

forming on the thin film transistor a metal wiring by using a photomask;

forming a first memory cell connected to the metal wiring;

forming on the thin film transistor a metal wiring by a droplet discharging method; and

forming a second memory cell connected to the metal wiring.

28. A method according to claim 27, further comprising a step of forming an antenna by a droplet discharging method after forming the second memory.

29. A method according to claim 28, wherein the antenna is formed on the semiconductor integrated circuit.

30. A method of manufacturing a semiconductor integrated circuit, comprising the steps of:

forming on an insulating substrate a thin film transistor;

forming on the thin film transistor a metal wiring by using a photomask;

forming a first memory cell connected to the metal wiring;

cutting a metal wiring on the thin film transistor by a laser cutting method; and

forming a second memory cell connected to the metal wiring.

31. A method according to claim 30, further comprising a step of forming an antenna by a droplet discharging method after forming the second memory.

32. A method according to claim 31, wherein the antenna is formed on the semiconductor integrated circuit.