III-nitride quantum-well field effect transistors

• US 20050133816A1
• Filed: 12/19/2003
• Published: 06/23/2005
• Est. Priority Date: 12/19/2003
• Status: Abandoned Application

• Current Assignee: III-N Technology, Inc., ILL Technology Company Limited
• Original Assignee: ILL Technology Company Limited
• Inventors: Li, Jing, Jiang, Hongxing, Lin, Jingyu, Fan, Zhaoyang
• Application Number:
  US10/741,268
• Publication Number:
  US 20050133816A1
• Time in Patent Office: Days
• US Class Current: 257/190
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material

Abstract

A transistor with improved device characteristics includes a substrate, a first buffer layer deposited on the substrate, a highly resistive epilayer deposited on the buffer layer, a second epilayer deposited on the highly resistive epilayer, a channel layer deposited on the second epilayer, an AlGaN alloy epilayer deposited on the channel layer, and source, gate, and drain connections deposited on the AlGaN alloy epilayer. The highly resistive epilayer may include AlGaN, InAlGaN, AlBN, or AlN compositions. The channel layer may include InGaN, graded InGaN, multilayers of InGaN and GaN, or GaN.

Claims

1. A transistor comprising:

a substrate;

a first buffer layer deposited on said substrate;

a first epilayer deposited on said buffer layer;

a second epilayer deposited on said first epilayer;

a GaN channel layer deposited on said second epilayer;

an AlGaN alloy epilayer deposited on said GaN channel layer;

a plurality of electrical connections deposited on said AlGaN alloy epilayer comprising;

a source connection, a gate connection and a drain connection thereby permitting a difference of electrical potential to be applied to said AlGaN alloy layer so as to permit operation as a transistor.

2. The transistor as set forth in claim 1 wherein said substrate is an insulating or semi-insulate substrate.

3. The transistor as set forth in claim 1 wherein said first epilayer comprises a highly resistive aluminum nitride (AlN) layer.

4. The transistor as set forth in claim 1 wherein said second epilayer comprises an aluminum nitride layer.

5. The transistor as set forth in claim 1 wherein said second epilayer comprises an aluminum gallium nitride layer.

6. The transistor as set forth in claim 1 wherein said GaN channel layer is generally less than 500 nanometers thick.

7. The transistor as set forth in claim 1 wherein said AlGaN alloy epilayer includes an n-type delta-doping.

8. The transistor as set forth in claim 1 wherein said AlGaN alloy epilayer includes an n-type doping.

9. The transistor as set forth in claim 1 wherein said GaN channel layer is backside doped.

10. The transistor as set forth in claim 1 further comprising a thin layer of AlN deposited between said GaN channel layer and said top AlGaN layer.

11. The transistor as set forth in claim 1 wherein said GaN channel layer is undoped.

12. The transistor as set forth in claim 1 wherein said GaN channel layer is intentionally doped.

13. The transistor as set forth in claim 1 wherein said the second epilayer has a graded aluminum composition.

14. A transistor comprising:

an insulating or semi-insulating substrate;

a first buffer layer deposited on said substrate;

a highly resistive aluminum nitride (AlN) epilayer deposited on said buffer layer;

an aluminum gallium nitride epilayer deposited on said highly resistive aluminum nitride (AlN) epilayer;

a GaN channel layer deposited on said aluminum gallium nitride epilayer;

an AlGaN alloy epilayer deposited on said GaN channel layer;

a plurality of electrical connections deposited on said AlGaN alloy epilayer comprising;

a source connection, a gate connection and a drain connection thereby permitting a difference of electrical potential to be applied to said AlGaN alloy layer so as to permit operation as a transistor.

15. The transistor as set forth in claim 14 wherein said GaN channel layer is generally less than 500 nanometers thick.

16. The transistor as set forth in claim 14 wherein said AlGaN alloy epilayer includes an n-type delta-doping.

17. The transistor as set forth in claim 14 wherein said AlGaN alloy epilayer includes an n-type doping.

18. The transistor as set forth in claim 14 wherein said GaN channel layer is backside doped.

19. The transistor as set forth in claim 14 further comprising a thin layer of AlN deposited between said GaN channel layer and said top AlGaN layer.

20. The transistor as set forth in claim 14 wherein said GaN channel layer is undoped.

21. The transistor as set forth in claim 14 wherein said GaN channel layer is intentionally doped.

22. The transistor as set forth in claim 14 wherein said aluminum gallium nitride epilayer has a graded aluminum composition.

23. A transistor comprising:

an insulating or semi-insulating substrate;

a first buffer layer deposited on said substrate;

a highly resistive aluminum nitride (AlN) epilayer deposited on said buffer layer;

an aluminum gallium nitride epilayer deposited on said highly resistive aluminum nitride (AlN) epilayer;

a backside doped GaN channel layer deposited on said aluminum gallium nitride epilayer;

an n-type doped AlGaN alloy epilayer deposited on said GaN channel layer;

a plurality of electrical connections deposited on said AlGaN alloy epilayer comprising;

a source connection, a gate connection and a drain connection thereby permitting a difference of electrical potential to be applied to said AlGaN alloy layer so as to permit operation as a transistor.

24. The transistor as set forth in claim 23 wherein said backside doped GaN channel layer is generally less than 500 nanometers thick.

25. The transistor as set forth in claim 23 wherein said n-type doped AlGaN alloy epilayer includes an n-type delta-doping.

26. The transistor as set forth in claim 23 further comprising a thin layer of AlN deposited between said backside doped GaN channel layer and said top AlGaN layer.

27. The transistor as set forth in claim 23 wherein said aluminum gallium nitride epilayer has a graded aluminum composition.

28. A transistor comprising:

a substrate;

a first buffer layer deposited on said substrate;

a first epilayer deposited on said buffer layer;

a second epilayer deposited on said first epilayer;

a channel layer deposited on said second epilayer;

an AlGaN alloy epilayer deposited on said channel layer;

a plurality of electrical connections deposited on said AlGaN alloy epilayer comprising;

a source connection, a gate connection and a drain connection thereby permitting a difference of electrical potential to be applied to said AlGaN alloy layer so as to permit operation as a transistor.

29. The transistor as set forth in claim 28 wherein said substrate is an insulating or semi-insulating substrate.

30. The transistor as set forth in claim 28 wherein said first epilayer comprises a highly resistive aluminum nitride (AlN) layer.

31. The transistor as set forth in claim 28 wherein said first epilayer comprises a highly resistive aluminum gallium nitride (AlGaN) layer.

32. The transistor as set forth in claim 28 wherein said first epilayer comprises a highly resistive indium aluminum gallium nitride (InAlGaN) layer.

33. The transistor as set forth in claim 28 wherein said first epilayer comprises a highly resistive aluminum boron nitride (AlBN) layer.

34. The transistor as set forth in claim 28 wherein said second epilayer comprises an aluminum nitride (AlN) layer.

35. The transistor as set forth in claim 28 wherein said second epilayer comprises an aluminum gallium nitride (AlGaN) layer.

36. The transistor as set forth in claim 28 wherein said second epilayer comprises an indium aluminum gallium nitride (InAlGaN) layer.

37. The transistor as set forth in claim 28 wherein said channel layer comprises a gallium nitride (GaN) layer.

38. The transistor as set forth in claim 28 wherein said channel layer comprises an indium gallium nitride (InGaN) layer.

39. The transistor as set forth in claim 28 wherein said channel layer comprises a graded indium gallium nitride (InGaN) layer.

40. The transistor as set forth in claim 28 wherein said channel layer comprises an indium gallium nitride (InGaN) layer and a gallium nitride (GaN) layer.

41. The transistor as set forth in claim 28 wherein said channel layer is generally less than 500 nanometers thick.

42. The transistor as set forth in claim 28 wherein said AlGaN alloy epilayer includes an n-type delta-doping.

43. The transistor as set forth in claim 28 wherein said AlGaN alloy epilayer includes an n-type doping.

44. The transistor as set forth in claim 28 wherein said channel layer is backside doped.

45. The transistor as set forth in claim 28 further comprising a thin layer of AlN deposited between said channel layer and said top AlGaN layer.

46. The transistor as set forth in claim 28 wherein said channel layer is undoped.

47. The transistor as set forth in claim 28 wherein said channel layer is intentionally doped.

48. The transistor as set forth in claim 28 wherein said the second epilayer has a graded aluminum composition.