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Semiconductor memory device having self-aligned charge trapping layer and method of manufacturing the same

  • US 20050133849A1
  • Filed: 12/01/2004
  • Published: 06/23/2005
  • Est. Priority Date: 12/17/2003
  • Status: Active Grant
First Claim
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1. A semiconductor memory device comprising:

  • a semiconductor substrate;

    a gate electrode formed on the substrate;

    a gate insulating layer separating the gate electrode from the substrate;

    conductive spacers separated across a groove, each conductive spacer comprising a bottom surface; and

    charge trapping layers respectively interposed between the substrate and one of the conductive spacers, and wherein each charge trapping layer is self-aligned with the bottom surface of a conductive spacer.

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