Semiconductor memory device having self-aligned charge trapping layer and method of manufacturing the same

• US 20050133849A1
• Filed: 12/01/2004
• Published: 06/23/2005
• Est. Priority Date: 12/17/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeon, Hee-seog, Kim, Yong-tae, Yoon, Seung-beom
• Granted Patent: US 7,345,336 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor memory device having a self-aligned charge trapping layer and a method of manufacturing the same in which a consistent length of an ONO layer is ensured. Here, an insulating stacked structure is self-aligned to a bottom surface of conductive spacers.

Claims

1. A semiconductor memory device comprising:

a semiconductor substrate;

a gate electrode formed on the substrate;

a gate insulating layer separating the gate electrode from the substrate;

conductive spacers separated across a groove, each conductive spacer comprising a bottom surface; and

charge trapping layers respectively interposed between the substrate and one of the conductive spacers, and wherein each charge trapping layer is self-aligned with the bottom surface of a conductive spacer.

2. The semiconductor memory device of claim 1, wherein the charge trapping layers have an equal length.

3. The semiconductor memory device of claim 1, wherein the length of each charge trapping layer is respectively equal to a bottom surface length for a corresponding conductive spacer.

4. The semiconductor memory device of claim 1, wherein each one of the charge trapping layers comprise a nitride layer.

5. The semiconductor memory device of claim 4, wherein each one of the charge trapping layers further comprises:

oxide layers formed above and below the nitride layer to form an ONO layer.

6. The semiconductor memory device of claim 1, wherein each one of the conductive spacers comprises a polysilicon layer.

7. The semiconductor memory device of claim 1, wherein the gate electrode further comprises:

a first gate electrode disposed in a lower portion of the groove between the conductive spacers; and

a second gate electrode formed in an upper portion of the groove and electrically connecting the pair of conductive spacers with the first gate electrode.

8. The semiconductor memory device of claim 7, wherein the gate insulating layer is formed laterally over the substrate and vertically up inner sidewalls defined by the conductive spacers;

and,

wherein the first gate electrode is vertically formed in the lower portion of the groove, such that an upper surface of the first gate electrode is parallel with an upper surface portion of the gate insulating layer.

9. The semiconductor memory device of claim 7, wherein the first gate electrode completely covers the lower portion of the groove.

10. The semiconductor memory device of claim 7, wherein the upper surface of the first gate electrode has a curved shaped.

11. The semiconductor memory of claim 7, wherein the conductive spacers are separated across a predetermined distance.

12. The semiconductor memory of claim 7, wherein the first gate electrode and the second gate electrode are formed from a material selected from a group of materials consisting of polysilicon, Al, W, WNx, Ta, TaN, Ru, Ti, TiN, Pt and any combination of these materials.

13. A method of manufacturing a semiconductor memory device comprising:

forming an insulating stacked structure including a charge trapping layer on a semiconductor substrate;

forming an intermediary material pattern on the insulating stacked structure;

forming conductive spacers on sidewalls of the intermediary material pattern, each conductive spacer having a bottom surface;

removing the intermediary material pattern and at least a portion of the charge trapping layer disposed below the intermediary material pattern, thereby forming a groove;

forming a gate electrode electrically connected to the conductive spacers within the groove; and

partially etching exposed portions of the insulating stacked material using the conductive spacers as etch masks, thereby forming a self-aligned charge trapping layer adjacent to a bottom surface of a conductive spacer.

14. The method of claim 13, wherein the insulating stacked structure is a tunnel oxide layer/charge trapping layer/charge stop layer.

15. The method of claim 13, wherein the forming of the intermediary material pattern comprises:

forming an insulating layer on the insulating stacked structure;

forming a photoresist pattern on the insulating layer to define the intermediary material pattern; and

removing the insulating layer using the photoresist pattern as an etch mask.

16. The method of claim 15, wherein a thickness of the insulating layer is about 2000 to 5000 Å

.

17. The method of claim 15, wherein the insulating stacked structure has an etch selectivity over that of the insulating layer.

18. The method of claim 15 further comprising:

after forming the intermediary material pattern, forming a silicon oxide layer to a thickness of about 30 to 80 Å

on exposed surfaces of the intermediary material pattern and the insulating stacked structure.

19. The method of claim 13, wherein the forming of the conductive spacers comprises:

depositing a conductive spacer material layer on exposed surfaces of the intermediary material pattern and the insulating stacked structure; and

forming the conductive spacers by anisotropically dry etching the conductive spacer material layer.

20. The method of claim 13, wherein bottom surface lengths for the conductive spacers are equal.

24. The method of claim 14, wherein the forming of the charge trapping layer pattern comprises:

removing the charge stop layer of the charge trapping layer using the conductive spacer as an etch mask; and

removing the charge trapping layer using the conductive spacer as an etch mask.

21. The method of 13, wherein the forming of the gate electrode comprises:

forming an interlayer insulating layer on exposed surfaces of the conductive spacers, the insulating stacked structure and the intermediary material pattern;

removing the intermediary material pattern via wet etch so as to expose a portion of the insulating stacked structure;

removing an exposed portion of the insulating stacked structure by wet etching or dry etching;

forming a gate insulating layer on the interlayer insulating layer and an exposed portion of the insulating stacked structure;

depositing a gate electrode material layer on the gate insulating layer, thereby filling at least a portion of the groove;

etching the gate electrode material layer, thereby exposing the upper plane of the interlayer insulating layer;

partially etching the gate electrode material layer, thereby forming a first gate electrode in a lower portion of the groove;

etching the gate insulating layer such that an upper surface of the gate insulating layer forms a plane with an upper surface of the first gate electrode; and

forming a second gate electrode in an upper portion of the groove and thereby electrically connecting the first gate electrode with the conductive spacers.

22. The method of claim 21, wherein the intermediary material has an etch selectivity over that of the interlayer insulating layer.

23. The method of claim 21, wherein the gate electrode material layer has an etch selectivity over that of the gate insulating layer:

25. A method of manufacturing a semiconductor memory device comprising:

forming a stacked layer with a silicon oxide layer/silicon nitride layer/silicon oxide layer structure on a semiconductor substrate;

forming an intermediary material pattern on the silicon oxide layer;

forming conductive spacers on sidewalls of the intermediary material pattern;

removing the intermediary material pattern and at least a portion of the stacked layer disposed below the intermediary material pattern, thereby forming a groove;

forming a gate electrode electrically connected to the conductive spacers within the groove;

etching exposed portions of an uppermost silicon oxide layer and the silicon nitride layer by using the conductive spacers as etch masks, thereby forming a self-aligned charge trapping layer adjacent to bottoms of the conductive spacers;

forming source and/or drain region(s) in the semiconductor substrate adjacent to the conductive spacers;

forming an interlayer insulating layer on exposed surfaces of the self-aligned charge trapping layer, the conductive spacers and the gate electrode;

etching the interlayer insulating layer to expose the drain region; and

forming a bit line in the interlayer insulating layer to contact the exposed drain region.

26. The method of claim 25, wherein the forming of the intermediary material pattern comprises:

forming a silicon nitride layer on the silicon oxide layer/silicon nitride layer/silicon oxide layer;

forming a photoresist pattern on the silicon nitride layer to define the intermediary material pattern; and

removing the silicon nitride layer using the photoresist pattern as an etch mask.

27. The method of claim 25, wherein the intermediary material pattern comprises a silicon nitride layer.

28. The method of claim 27, wherein a thickness of the silicon nitride layer is about 2000 to 5000 Å

.

29. The method of claim 25, wherein the forming of the conductive spacers comprises:

depositing a conductive spacer material layer on exposed surfaces of the stacked layer and the intermediary material pattern; and

etching the conductive spacer material layer via anisotropic dry etching.

30. The method of claim 25, wherein bottom lengths of the conductive spacers are equal.

31. The method of claim 25, wherein the forming of the gate electrode comprises:

forming an interlayer insulating layer on exposed surfaces of the conductive spacers, the stacked layer and the intermediary material pattern;

removing the intermediary material pattern via wet etch so as to expose a portion of the silicon oxide layer;

removing the stacked layer by wet etching or dry etching;

forming a gate oxide layer on the interlayer insulating layer and an exposed portion of the stacked structure;

depositing a gate electrode material layer on the gate insulating layer, thereby filling the groove;

etching the gate electrode material layer, thereby exposing an upper surface of the interlayer insulating layer;

partially etching the gate electrode material layer, thereby forming a first gate electrode in a lower portion of the groove;

etching the gate oxide layer such that an upper surface of the gate insulating layer forms a plane with an upper surface of the first gate electrode; and

forming a second gate electrode in an upper portion of the groove for electrically connecting the first gate electrode with the conductive spacers.

32. The method of claim 31 further comprising:

after forming the gate oxide layer, thermally treating the gate oxide layer at a temperature of between about 900 to 1100°

C.

33. The method of claim 25, wherein the forming of the charge trapping layer comprises:

removing the upper silicon oxide layer on the silicon nitride layer by using the conductive spacers as an etch mask; and

removing the silicon nitride layer by using the conductive spacers as an etch mask.