Semiconductor memory device having self-aligned charge trapping layer and method of manufacturing the same
First Claim
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1. A semiconductor memory device comprising:
- a semiconductor substrate;
a gate electrode formed on the substrate;
a gate insulating layer separating the gate electrode from the substrate;
conductive spacers separated across a groove, each conductive spacer comprising a bottom surface; and
charge trapping layers respectively interposed between the substrate and one of the conductive spacers, and wherein each charge trapping layer is self-aligned with the bottom surface of a conductive spacer.
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Abstract
A semiconductor memory device having a self-aligned charge trapping layer and a method of manufacturing the same in which a consistent length of an ONO layer is ensured. Here, an insulating stacked structure is self-aligned to a bottom surface of conductive spacers.
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Citations
33 Claims
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1. A semiconductor memory device comprising:
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a semiconductor substrate;
a gate electrode formed on the substrate;
a gate insulating layer separating the gate electrode from the substrate;
conductive spacers separated across a groove, each conductive spacer comprising a bottom surface; and
charge trapping layers respectively interposed between the substrate and one of the conductive spacers, and wherein each charge trapping layer is self-aligned with the bottom surface of a conductive spacer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of manufacturing a semiconductor memory device comprising:
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forming an insulating stacked structure including a charge trapping layer on a semiconductor substrate;
forming an intermediary material pattern on the insulating stacked structure;
forming conductive spacers on sidewalls of the intermediary material pattern, each conductive spacer having a bottom surface;
removing the intermediary material pattern and at least a portion of the charge trapping layer disposed below the intermediary material pattern, thereby forming a groove;
forming a gate electrode electrically connected to the conductive spacers within the groove; and
partially etching exposed portions of the insulating stacked material using the conductive spacers as etch masks, thereby forming a self-aligned charge trapping layer adjacent to a bottom surface of a conductive spacer. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 24)
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21. The method of 13, wherein the forming of the gate electrode comprises:
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forming an interlayer insulating layer on exposed surfaces of the conductive spacers, the insulating stacked structure and the intermediary material pattern;
removing the intermediary material pattern via wet etch so as to expose a portion of the insulating stacked structure;
removing an exposed portion of the insulating stacked structure by wet etching or dry etching;
forming a gate insulating layer on the interlayer insulating layer and an exposed portion of the insulating stacked structure;
depositing a gate electrode material layer on the gate insulating layer, thereby filling at least a portion of the groove;
etching the gate electrode material layer, thereby exposing the upper plane of the interlayer insulating layer;
partially etching the gate electrode material layer, thereby forming a first gate electrode in a lower portion of the groove;
etching the gate insulating layer such that an upper surface of the gate insulating layer forms a plane with an upper surface of the first gate electrode; and
forming a second gate electrode in an upper portion of the groove and thereby electrically connecting the first gate electrode with the conductive spacers. - View Dependent Claims (22, 23)
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25. A method of manufacturing a semiconductor memory device comprising:
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forming a stacked layer with a silicon oxide layer/silicon nitride layer/silicon oxide layer structure on a semiconductor substrate;
forming an intermediary material pattern on the silicon oxide layer;
forming conductive spacers on sidewalls of the intermediary material pattern;
removing the intermediary material pattern and at least a portion of the stacked layer disposed below the intermediary material pattern, thereby forming a groove;
forming a gate electrode electrically connected to the conductive spacers within the groove;
etching exposed portions of an uppermost silicon oxide layer and the silicon nitride layer by using the conductive spacers as etch masks, thereby forming a self-aligned charge trapping layer adjacent to bottoms of the conductive spacers;
forming source and/or drain region(s) in the semiconductor substrate adjacent to the conductive spacers;
forming an interlayer insulating layer on exposed surfaces of the self-aligned charge trapping layer, the conductive spacers and the gate electrode;
etching the interlayer insulating layer to expose the drain region; and
forming a bit line in the interlayer insulating layer to contact the exposed drain region. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33)
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Specification