Three-dimensional memory cells and peripheral circuits

• US 20050133875A1
• Filed: 01/07/2005
• Published: 06/23/2005
• Est. Priority Date: 04/08/2002
• Status: Active Grant

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Granted Patent: US 7,763,911 B2
• Time in Patent Office: Days
• US Class Current: 257/390
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 29/76 Unipolar devices , e.g. field effect transistors

Abstract

The present invention discloses several preferred mask-programmable 3-D memory (3D-MPROM) structures, including pillar-shaped 3D-MPROM, natural-junction 3D-MPROM, interleaved 3D-MPROM, and separate 3D-MPROM. The present invention also makes further improvements to its peripheral circuits. The use of sense-amplifier can significantly lower the leakage-current requirement on the 3D-ROM memory cell. Self-timing can improve the 3D-ROM speed and reduce its power consumption.

Claims

1. A non-electrically-programmable three-dimensional memory (NEP-3DM), comprising:

a substrate including transistors thereon;

at least a first and a second memory levels, said first and second memory levels being stacked on top of said substrate and said first memory level, respectively;

a plurality of inter-level connecting vias and/or contact vias, said vias connecting said memory levels with said substrate;

said memory levels comprising a plurality of memory cells, said memory cell further comprising a first address-selection line with a first width, a second address-selection line with a second width and a mask-programmable 3D-ROM layer.

2. The NEP-3DM according to claim 1, wherein said first and second memory levels share at least one address-selection line.

3. The NEP-3DM according to claim 1, wherein one dimension of said 3D-ROM layer is equal to said first width;

and the other dimension of said 3D-ROM layer is equal to said second width.

4. The NEP-3DM according to claim 1, wherein said 3D-ROM layer is a natural junction between said first and second address-selection lines, a first portion of said natural junction located in said first address-selection line, a second portion of said natural junction located in said second address-selection line.

5. The NEP-3DM according to claim 1, wherein at least a selected one of said address-selection lines comprises a semiconductor material doped by metallic ions.

6. The NEP-3DM according to claim 1, wherein said 3D-ROM layer is a polarized layer comprising at least two sub-layers with different base materials.

7. The NEP-3DM according to claim 1, wherein said 3D-ROM layer has a polarized structure, the interface between said 3D-ROM layer and said first address-selection line being different from the interface between said 3D-ROM layer and said second address-selection line.

8. The NEP-3DM according to claim 1, wherein said memory cell is a seamless 3D-ROM cell, the interfaces between said 3D-ROM layer and said first address-selection line and between said 3D-ROM layer and said second address-selection line not exposed to any substantial material-removal processing step.

9. The NEP-3DM according to claim 1, wherein said memory cell is a quasi-seamless 3D-ROM cell, the interfaces between at least a portion of said 3D-ROM layer and said first address-selection line and between said portion of said 3D-ROM layer and said second address-selection line not exposed to any substantial material-removal processing step.

10. The NEP-3DM according to claim 1, wherein said memory cell comprises a large-bandgap semiconductor material, whereby said NEP-3DM supports in high-temperature operation.

11. The NEP-3DM according to claim 1, wherein said memory cell comprises a micro-crystalline semiconductor material.

12. A non-electrically-programmable three-dimensional memory (NEP-3DM), comprising:

a substrate circuit, said substrate circuit comprising a peripheral circuit, said peripheral circuit further comprising a plurality of data sense-amplifiers (S/A);

at least an NEP-3DM level stacked on said substrate circuit, said NEP-3DM level comprising at least one unit array, said unit array further comprising a plurality of NEP-3DM cells, data-bit lines and data-word lines;

a plurality of inter-level connecting vias and/or contact vias, said vias connecting said data-bit line with said data S/A.

13. The NEP-3DM according to claim 12, further comprising a constant dc-source, and a plurality of switches, each bit line in said unit array being connected to said constant dc-source through a selected one of said switches, all switches associated with said unit array being controlled by a single control signal.

14. The NEP-3DM according to claim 12, wherein:

said data S/A further comprises a data S/A-enable (SE) signal; and

said data S/A samples the voltage on said data-bit line when said SE signal is asserted.

15. The NEP-3DM according to claim 14, wherein all data S/A in said unit array share a single data SE signal.

16. The NEP-3DM according to claim 14, further comprising a first timing bit line and an associated first timing S/A, whereby the output from said first timing S/A eventually toggles said data SE signal and starts the data sampling for said data-bit line.

17. The NEP-3DM according to claim 14, further comprising a second timing bit line and an associated second timing S/A, whereby the output from said second timing S/A eventually toggles said data SE signal and stops the data sampling for said data-bit line.

18. The NEP-3DM according to claim 12, further comprising a dummy-bit line, wherein

said data S/A is a differential S/A with a first input and a second input;

said data-bit line is connected with said first input; and

said dummy-bit line is connected with said second input.

19. The NEP-3DM according to claim 12, wherein

said NEP-3DM level comprises a plurality of NEP-3DM cells, the read voltage (V_R) for said NEP-3DM cell being larger than the largest supply voltage for said NEP-3DM;

said substrate circuit further comprises a V_R-generating block.

20. The NEP-3DM according to claim 12, wherein the total number of data-bit lines in said unit array is larger than the total number of data-word lines in said unit array.