Lead frame structure with aperture or groove for flip chip in a leaded molded package

• US 20050133893A1
• Filed: 02/04/2005
• Published: 06/23/2005
• Est. Priority Date: 04/11/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Chung-Lin Wu, Rajeev Joshi
• Inventors: Joshi, Rajeev, Wu, Chung-Lin
• Granted Patent: US 7,081,666 B2
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/37011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/37099 Material
• CPC Class Codes: H01L 2224/40095 Kinked
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/73255 Bump and strap connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84 using a strap connector
• CPC Class Codes: H01L 2224/92226 the second connecting process involving a strap connector
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

Claims

1. A semiconductor die package comprising:

(a) a semiconductor die including a first surface and a second surface;

(b) a leadframe structure comprising a die attach region and a plurality of leads extending away from the die attach region, wherein the die attach region includes one or more apertures extending through the die attach region and being oriented generally perpendicular to the orientations of the leads in the plurality of leads, and wherein the semiconductor die is mounted on the die attach region of the leadframe structure; and

(c) a molding material that is around at least portions of the die attach region of the leadframe structure and the semiconductor die, and wherein the molding material is also within the one or more apertures in the die attach region of the lead frame structure.

2. The semiconductor die package of claim 1 wherein the die attach region comprises at least two slots aligned from end to end.

3. The semiconductor die package of claim 1 wherein the lead frame structure includes a source lead structure with a plurality of source leads, the plurality of source leads extending laterally away from the molding material.

4. The semiconductor die package of claim 1 wherein the lead frame structure includes a source lead structure, a gate lead structure, and a dummy lead structure.

5. The semiconductor die package of claim 1 wherein the semiconductor die includes a drain region at the second surface, and a source region and a gate region at the first surface, and wherein the leadframe structure includes a source lead structure coupled to the source region and including a plurality of source leads, the plurality of source leads extending laterally away from the molding material, and a gate lead structure coupled to the gate region and including a gate lead extending laterally away from the molding material, and wherein the semiconductor die package further includes a drain clip coupled to the drain region of the semiconductor die.

6. The semiconductor die package of claim 1 wherein the semiconductor die includes a drain region at the second surface, and a source region and a gate region at the first surface, and wherein the semiconductor die package further comprises a drain clip coupled to a drain region in the semiconductor die.

7. The semiconductor die package of claim 1 wherein the one or more apertures are in the form of elongated slots.

8. The semiconductor die package of claim 1 wherein the leadframe structure comprises copper or a copper alloy.

9. The semiconductor die package of claim 1 wherein the die attach region further includes a plurality of grooves formed in the leadframe structure.

10. The semiconductor die package of claim 9 wherein the leadframe structure comprises copper or a copper alloy.

11. A leadframe structure comprising:

a die attach region;

a plurality of leads extending away from the die attach region; and

one or more apertures in the die attach region and extending through the die attach region, and wherein the one or more apertures are oriented generally perpendicular to the leads in the plurality of leads.

12. The leadframe structure of claim 11 wherein the apertures are in the form of elongated slots.

13. The leadframe structure of claim 11 wherein the apertures are in the form of elongated slots, and wherein at least two of the elongated slots are aligned from end to end.

14. The leadframe structure of claim 11 further comprising a plurality of grooves formed in the die attach region.

15. A method for forming a semiconductor die package, the method comprising:

(a) attaching a semiconductor die including a first surface and a second surface to a die attach region in a leadframe structure using solder, the leadframe structure comprising one or more apertures extending through the die attach region and a plurality of leads extending away from the die attach region, and wherein the one or more apertures are oriented generally perpendicular to the orientations of the leads in the plurality of leads; and

(b) molding a molding material at least partially around the semiconductor die and the die attach region, wherein the molding material passes into the one or more apertures in the die attach region of the leadframe structure.

16. The method of claim 15 wherein the semiconductor die comprises a vertical power MOSFET.

17. The method of claim 15 wherein the leadframe structure comprises copper.

18. The method of claim 15 wherein the apertures are in the form of elongated slots, and wherein at least two of the elongated slots are aligned from end to end.

19. The method of claim 15 wherein the leadframe structure comprises copper or a copper alloy.

20. A semiconductor die package comprising:

(a) a semiconductor die including a first surface and a second surface;

(b) a leadframe structure comprising a die attach region and a plurality of leads extending away from the die attach region, wherein the die attach region includes one or more grooves in the die attach region, and wherein the semiconductor die is mounted on the die attach region of the leadframe structure using solder that is disposed in the one or more grooves; and

(c) a molding material that is around at least portions of the die attach region of the leadframe structure and the semiconductor die.

21. The semiconductor die package of claim 20 wherein the die attach region comprises at least one aperture extending through the die attach region.

22. The semiconductor die package of claim 21 wherein the aperture is in the form of a slot, the slot being oriented generally perpendicular to the leads in the plurality of leads.

23. The semiconductor die package of claim 21 wherein the aperture is in the form of a slot, the slot being oriented generally parallel to the leads in the plurality of leads.