Component packaging apparatus, systems, and methods

• US 20050133909A1
• Filed: 12/18/2003
• Published: 06/23/2005
• Est. Priority Date: 12/18/2003
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Franca-Neto, Luiz M.
• Application Number:
  US10/739,468
• Publication Number:
  US 20050133909A1
• Time in Patent Office: Days
• US Class Current: 257/724
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01Q 23/00 Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: H01Q 9/16 with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole H01Q9/44 takes precedence
• CPC Class Codes: H04W 88/02 Terminal devices

Abstract

An apparatus and a system, as well as a method and an article, may include operating a processor included in a die having at least one scalable component of a circuit, including one or more radio frequency circuits, in electrical communication with a non-scalable component of the circuit located on a structure, such as a substrate or package to which the die may be coupled. The die may be constructed so that it does not include another non-scalable component of the circuit.

Claims

1. An apparatus, including:

a die having at least one scalable component of a circuit; and

a structure having at least one non-scalable component of the circuit,

wherein the die does not include another non-scalable component of the circuit.

2. The apparatus of claim 1, wherein the structure does not include another scalable component of the circuit.

3. The apparatus of claim 1, wherein the die is attached to the structure.

4. The apparatus of claim 1, wherein the die is attached to the structure with at least one controlled collapse chip connection.

5. The apparatus of claim 1, wherein the scalable component includes a transistor.

6. The apparatus of claim 1, wherein the structure includes a flip-chip package.

7. The apparatus of claim 1, wherein the at least one non-scalable component includes at least one of a transformer, a transmission line, an inductor, a capacitor, and a resistor.

8. The apparatus of claim 1, wherein the circuit includes at least one of a transceiver, a transmitter, a receiver, an amplifier, a synthesizer, an oscillator, and a mixer.

9. The apparatus of claim 1, wherein the at least one non-scalable component includes a trace included in the structure.

10. The apparatus of claim 9, wherein the trace is included in at least one of a transmission line, an inductor, and a transformer.

11. An apparatus, including:

a die having a plurality of scalable transistors included in a radio frequency circuit; and

a package having a plurality of non-scalable components included in the radio frequency circuit, including a first inductor, wherein the die does not include a second inductor of the radio frequency circuit.

12. The apparatus of claim 11, wherein the plurality of non-scalable components include at least one of a second inductor, and a transformer to couple at least one of the plurality of scalable transistors to an antenna.

13. The apparatus of claim 12, wherein the package includes a flip-chip package, and wherein the die is attached to the flip-chip package by a controlled collapse chip connection.

14. A system, including:

a die having a processor and at least one scalable component of a circuit; and

a structure having at least one non-scalable component of the circuit,

wherein the die does not include another non-scalable component of the circuit.

15. The system of claim 14, further including:

a dipole antenna to couple to the circuit.

16. The system of claim 14, wherein the structure does not include another scalable component of the circuit.

17. The system of claim 14, wherein the die is attached to the structure.

18. The system of claim 14, wherein the scalable component includes a transistor.

19. The system of claim 14, wherein the at least one non-scalable component includes at least one of a transformer, a transmission line, an inductor, a capacitor, and a resistor.

20. The system of claim 14, wherein the circuit includes a radio frequency circuit.

21. The system of claim 14, further including:

a memory coupled to the processor and the circuit, wherein the circuit includes a data transceiver.

22. A method, including:

operating a processor included in a die having at least one scalable component of a circuit in electrical communication with a non-scalable component of the circuit, wherein the die does not include another non-scalable component of the circuit.

23. The method of claim 22, further including:

sharing data between the processor and the circuit.

24. The method of claim 23, further including:

receiving the data to store in a memory coupled to the processor.

25. The method of claim 23, further including:

transmitting the data stored in a memory coupled to the processor.

26. The method of claim 22, wherein the circuit includes a data transceiver.

27. An article comprising a machine-accessible medium having associated information, wherein the information, when accessed, results in a machine performing:

simulating operating a processor included in a die having at least one scalable component of a circuit in electrical communication with a non-scalable component of the circuit, wherein the die does not include another non-scalable component of the circuit; and

generating a human-perceivable result of the simulating.

28. The article of claim 27, wherein the die includes a processor coupled to the circuit.

29. The article of claim 28, wherein the processor is to share data with the circuit.

30. The article of claim 27, wherein the information, when accessed, results in the machine performing:

simulating sharing data between the processor and the circuit including a data transceiver.

31. The article of claim 30, wherein the information, when accessed, results in the machine performing:

simulating receiving the data to store in a memory coupled to the processor.

32. The article of claim 30, wherein the information, when accessed, results in the machine performing:

simulating transmitting the data stored in a memory coupled to the processor.