Transistor device

• US 20050133917A1
• Filed: 12/17/2003
• Published: 06/23/2005
• Est. Priority Date: 12/17/2003
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.), Oregon State University (Oregon University System)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.), Oregon State University (Oregon University System)
• Inventors: Hoffman, Randy, Wager, John
• Granted Patent: US 7,026,713 B2
• Time in Patent Office: Days
• US Class Current: 257/749
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A transistor device includes a channel of p-type substantially transparent delafossite material. Source and drain contacts are interfaced to the channel. Gate dielectric is between a gate contact and the channel.

Claims

1. A transistor device, comprising:

a channel of p-type substantially transparent delafossite material;

a source contact interfaced to said channel;

a drain contact interfaced to said channel;

a gate contact; and

gate dielectric between said gate contact and said channel.

2. The device of claim 1, wherein said p-type delafossite material comprises undoped delafossite material.

3. The device of claim 1, wherein said gate contact is formed upon a substrate, said gate dielectric is formed upon said gate contact, and said channel is formed upon said gate dielectric.

4. The device of claim 3, wherein said source contact and said drain contact comprise co-planar contacts.

5. The device of claim 3, wherein said source contact and said drain contact comprise staggered contacts.

6. The device of claim 3, wherein said gate, source and drain contacts are patterned to form a circuit interconnect pattern.

7. The device of claim 6, further comprising an n-type transparent channel transistor connected through the circuit pattern to form a CMOS circuit.

8. The device of claim 7, further comprising an integrated device, wherein the integrated device attaches or is formed upon a backside of the substrate.

9. The device of claim 3, further comprising an additional dielectric and an additional gate contact formed upon said channel and said source and drain contacts.

10. The device of claim 1, wherein the delafossite material is selected from the group consisting of CuScO₂, CuAlO₂, CuYO₂, CuFeO₂, CuCrO₂, CuGaO₂, CuInO₂, AgCoO₂, AgGaO₂, AgInO₂, AgScO₂, and AgCrO₂.

11. The device of claim 9, wherein:

said gate dielectric is formed from a material selected from the group consisting of SiO₂, Si₃N₄, Al₂O₃, Ta₂O₅, HfO₂, ZrO₂; and

said source, drain and gate contacts are formed from a material selected from the group consisting of doped semiconductors and metals.

12. The device of claim 10, wherein said source, drain and gate contacts comprise a doped semiconductor selected from the group consisting of GaN, BaCu₂S₂, NiO, Cu₂O, CuScO₂, CuAlO₂, CuYO₂, CuFeO₂, CuCrO₂, CuGaO₂, CuInO₂, AgCoO₂, AgGaO₂, AgInO₂, AgScO₂, AgCrO₂.

13. The device of claim 1, wherein said source and drain contacts are formed upon a substrate, said channel is formed upon the substrate, and said gate dielectric is formed upon said source and drain contacts and said channel.

14. The device of claim 13, wherein said source contact and said drain contact comprise co-planar contacts.

15. The device of claim 14, wherein said source contact and said drain contact comprise staggered contacts.

16. The device of claim 13, wherein said gate, source and drain contacts are patterned to form a circuit interconnect pattern.

17. The device of claim 16, further comprising an n-type transparent channel transistor connected through the circuit pattern to form a CMOS circuit.

18. The device of claim 17, further comprising an integrated device, wherein the integrated device attaches or is formed upon a backside of the substrate.

19. The device of claim 13, wherein the delafossite material is selected from the group consisting of CuScO₂, CuAlO₂, CuYO₂, CuFeO₂, CuCrO₂, CuGaO₂, CuInO₂, AgCoO₂, AgGaO₂, AgInO₂, AgScO₂, and AgCrO₂.

20. The device of claim 19, wherein:

said gate dielectric is formed from a material selected from the group consisting of SiO₂, Si₃N₄, Al²O₃, Ta₂O₅, HfO₂, ZrO₂; and

said source, drain and gate contacts are formed from a material selected from the group consisting of doped semiconductors and metals.

21. The device of claim 20, wherein said source, drain and gate contacts comprise a doped semiconductor selected from the group consisting of GaN, BaCu₂S₂, NiO, Cu₂O, CuScO₂, CuAlO₂, CuYO₂, CuFeO₂, CuCrO₂, CuGaO₂, CuInO₂, AgCoO₂, AgGaO₂, AgInO₂, AgScO₂, AgCrO₂.

22. The device of claim 19, wherein each of said source, drain and gate contacts, and said gate dielectric is formed from a transparent material such that the device comprises a transparent device.

23. The device of claim 1, wherein said p-type substantially transparent delafossite material comprises undoped or lightly doped delafossite material.

24. The device of claim 1, formed as a thin film device.

25. A thin film transistor device, comprising:

a thin film channel of undoped or lightly doped p-type delafossite material, the delafossite material being substantially transparent; and

means for controlling conduction in said thin film channel.

26. The device of claim 25, wherein said means for controlling comprise gate, source and drain thin film contacts.

27. The device of claim 26, wherein said gate source and drain thin film contacts are patterned to form a circuit interconnect pattern.

28. The device of claim 27, further comprising an n-type transparent channel thin film transistor connected through the circuit pattern to form a CMOS circuit.

29. The device of claim 28, further comprising an integrated device, wherein the integrated device attaches or is formed upon a backside of a substrate upon which the CMOS circuit is formed.

30. A thin film transistor device, comprising:

a thin film channel of substantially transparent p-type material;

a thin film source contact interfaced to said channel;

a thin film drain contact interfaced to said channel;

a thin film gate contact; and

thin film gate dielectric between said thin film gate contact and said channel;

wherein materials for said thin film channel, said thin film source contact, and said thin film drain contact are selected so that a work function of materials of the thin film source and drain contacts is nearly equal to or greater than an ionization potential of the p-type material of the thin film channel.

31. The device of claim 30, wherein the transparent p-type material comprises a delafossite material.

32. The device of claim 31, wherein the delafossite thin film comprises an undoped delafossite material.

33. The device of claim 31, wherein the delafossite material is selected from the group consisting of CuScO₂, CuAlO₂, CuYO₂, CuFeO₂, CuCrO₂, CuGaO₂, CuInO₂, AgCoO₂, AgGaO₂, AgInO₂, AgScO₂, and AgCrO₂.

34. The device of claim 32, wherein:

said thin film gate dielectric is formed from a material selected from the group consisting of SiO₂, Si₃N₄, Al₂O₃, Ta₂O₅, HfO₂, ZrO₂; and

said thin film source, drain and gate contacts are formed from a material selected from the group consisting of doped semiconductors and metals.

35. The device of claim 34, wherein said thin film source, drain and gate contacts comprise a doped semiconductor selected from the group consisting of GaN, BaCu₂S₂, NiO, Cu₂O, CuScO₂, CuAlO₂, CuYO₂, CuFeO₂, CuCrO₂, CuGaO₂, CuInO₂, AgCoO₂, AgGaO₂, AgInO₂, AgScO₂, AgCrO₂.

36. The device of claim 30, wherein each of said thin film source, drain and gate contacts, and said thin film gate dielectric is formed from a transparent material such that the device comprises a transparent device.

37. A method of using a transistor device, the transistor device comprising a channel of p-type substantially transparent delafossite material, a source contact interfaced to said channel, a drain contact interfaced to said channel, a gate contact, and a gate dielectric between said gate contact and said channel, the method comprising:

arranging the transistor device with additional transistor devices;

providing voltages to said source, drain and gate contacts to induce conduction in said channel.

38. The method of claim 37, wherein said providing voltages comprises providing a negative voltage to said gate to draw holes from one or both of said source and drain contacts.

39. The method of claim 38, further comprising providing additional voltages to operate the transistor device, said providing additional voltages comprising a providing a turn-off voltage to said gate contact.

40. The method of claim 37, wherein said arranging arranges the transistor device with additional transistor devices in a switch circuit configuration.

41. The method of claim 37, wherein said arranging arranges the transistor device with additional transistor devices in an amplifier circuit configuration.

42. The method of claim 37, wherein said arranging arranges the transistor device with additional transistor devices in a load circuit configuration.

43. A method of forming a transistor device, the method comprising:

in an appropriate sequence for a desired transistor configuration, depositing thin film layers including thin film gate, source, and drain contacts, gate dielectric and a substantially transparent delafossite channel; and

at appropriate times during the appropriate sequence, patterning the thin film layers.

44. The method of claim 43, wherein depositing comprises applying solution-based deposition techniques.

45. The method of claim 44, wherein said solution-based deposition techniques comprise direct write techniques.

46. The method of claim 45, wherein said patterning comprises a lithography and etching process.

47. The method of claim 45, wherein said patterning comprises a direct-write patterning.