Semiconductor device and method for manufacturing the same

• US 20050133923A1
• Filed: 01/24/2005
• Published: 06/23/2005
• Est. Priority Date: 02/02/2001
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Yoshie, Toru
• Granted Patent: US 7,224,064 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: B24B 37/04 designed for working plane surfaces
• CPC Class Codes: B24B 57/02 for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76835 : Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 2221/1047 : the air gaps being formed by pores in the dielectric
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device featuring higher integration and higher speed at the same time, and a manufacturing method for the same are provided. The semiconductor device is constructed by a semiconductor substrate on which a plurality of elements making up, for example, a logic type device, have been formed, a first interlayer insulating film serving as a first insulating film formed on the semiconductor substrate, a plurality of groove patterns provided in the first interlayer insulating film, lower interconnections formed by embedding electroconductive films, which are composed of an electroconductive material, including copper (Cu) or the like, in the groove patterns, and first porous portions that are selectively provided in the portions of the first interlayer insulating film having the lower interconnections formed therein, the portions being in contact with the lower interconnections. This arrangement provides an interlayer insulating film that exhibits satisfactory mechanical strength and thermal conductivity in a semiconductor device employing an interlayer insulating film composed of an insulating material having a low dielectric constant.

Claims

1. A semiconductor device, comprising:

a substrate;

a first insulating film formed on the substrate, the first insulating film including a first porous portion having a first groove, a second porous portion having a second groove and a nonporous portion adjoining the porous portions;

a plurality of interconnections including a first conductive pattern disposed in the first groove and a second conductive pattern disposed in the second groove.

2. A semiconductor device according to claim 1, wherein the first porous portions are the first insulating films having a plurality of voids formed therein.

3. A semiconductor device according to claim 1, wherein

a plurality of the lower interconnections comprise third, fourth, fifth, and sixth conductive patterns provided so that they are spaced away from each other,

the distance between the third conductive pattern and the fourth conductive pattern is shorter than the distance between the fifth conductive pattern and the sixth conductive pattern,

the first insulating film between the third conductive pattern and the fourth conductive pattern comprises the first porous portions in contact with both the third and fourth conductive patterns, and

the first insulating film between the fifth conductive pattern and the sixth conductive pattern comprises the first porous portion in contact with the fifth conductive pattern, the first porous portion in contact with the sixth conductive pattern, and the first nonporous portion provided between the first porous portions in contact with the fifth and sixth conductive patterns.

4. A semiconductor device according to claim 3, wherein the distance between the third conductive pattern and the fourth conductive pattern is about 800 nm or less.

5. A semiconductor device according to claim 1, wherein the conductive patterns are composed of an electroconductive material, including Cu.

6. A semiconductor device according to claim 1, wherein the porous portions are composed of insulating films that have been perforated by about 70% of the entire area thereof.

7. A semiconductor device according to claim 1, wherein the insulating films are the insulating films to which an additive substance has been added.

8. A semiconductor device comprising:

a plurality of grooves formed in a first insulating film on a substrate; and

a plurality of lower interconnections embedded in the grooves,

wherein the first insulating film having a plurality of the lower interconnections formed therein comprises first porous portions provided in contact with the side surfaces of a plurality of the lower interconnections, first nonporous portions provided between the first porous portions, and second nonporous portions provided in contact with the bottom surfaces of a plurality of the lower interconnections.

9. A semiconductor device comprising:

a substrate;

a first insulating film formed on the substrate, the first insulating film including a first porous portion having a first groove, a second porous portion having a second groove and a nonporous portion adjoining the porous portions;

a plurality of lower interconnections including a first conductive pattern disposed in the first groove and a second conductive pattern disposed in the second groove;

second insulating films formed on the first insulating films and a plurality of lower interconnections;

openings formed in the second insulating films on a plurality of lower interconnections; and

upper interconnections that are embedded in the openings and electrically connected with a plurality of lower interconnections,

wherein the second insulating films in which the upper interconnections are formed comprise second porous portions provided in contact with the upper interconnections, and third nonporous portions provided in contact with the second porous portions.

10. A semiconductor device according to claim 9, wherein the second porous portions are composed of the second insulating films comprising a plurality of voids.

11. A semiconductor device according to claim 9, wherein

the openings comprise grooves and connecting holes extending from the bottom surfaces of the grooves to a plurality of the lower interconnections,

the upper interconnections comprise upper layer conductive patterns embedded in the grooves, and connecting plugs for electrically connecting the upper layer conductive patterns and a plurality of the lower interconnections, and

the second porous portions provided in contact with the side surfaces of the upper interconnections, the third nonporous portions provided in contact with the second porous portions, and fourth nonporous portions that are in contact with the bottom surfaces of the upper layer conductive patterns and are provided in the second insulating films are included.

12. A semiconductor device according to claim 9, wherein the conductive patterns are composed of an electroconductive material, including Cu.

13. A semiconductor device according to claim 9, wherein the porous portions are composed of insulating films that have been perforated by about 70% of the entire area thereof.

14. A semiconductor device according to claim 9, wherein the insulating films are the insulating films to which an additive substance has been added.

15-30. -30. (canceled)