Self-limiting pulse width modulation regulator

• US 20050134243A1
• Filed: 12/22/2004
• Published: 06/23/2005
• Est. Priority Date: 08/11/2003
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Weiner, Albert S.
• Granted Patent: US 7,002,386 B2
• Time in Patent Office: Days
• US Class Current: 323/282
• CPC Class Codes: H03K 3/017 Adjustment of width or dutycycle of pulses pulse width modulation H03K7/08 ; to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: H03K 5/082 with an adaptive threshold
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

A self-adjusting PWM regulator which minimizes undershoot and overshoot conditions is disclosed. The regulator includes a charge pump, a voltage comparator circuit, and a latch circuit. The input of the voltage comparator circuit includes an output of the charge pump. The input of the latch circuit includes an output from the voltage comparator circuit. The latch circuit includes a pair of SR latches coupled to a pair of AND/OR gates. The latch circuit transmits a first signal to the charge pump to prevent an overshoot condition if the output from the voltage comparator circuit is in a first state, and transmits a second signal to prevent an undershoot condition if the output from the voltage comparator circuit is in a second state. This keeps the charge pump adjusted within the limits of its control.

Claims

1-24. -24. (canceled)

25. A pulse width modulation regulator, comprising:

a first controller, wherein the first controller receives as input a clock signal and a first control signal and outputs a first pulse width modulated signal;

a second controller, wherein the second controller receives as input an inverse of the clock signal and a second control signal and outputs a second pulse width modulated signal,

wherein the first control signal maintains the second pulse width modulated signal at a first state when the first pulse width modulated signal has not increased to a desired pulse width,

wherein the second control signal maintains the first pulse width modulated signal at a second state when the second pulse width modulated signal has not decreased to the desired pulse width; and

an OR gate for receiving as input the first and second pulse width modulated signals and for providing an output signal.

26. The regulator of claim 25, wherein at least the first or the second controller comprises:

a charge pump;

a comparator circuit coupled to the charge pump, the comparator circuit for providing a pulse width modulated signal; and

a latch circuit coupled to the charge pump for ensuring that the charge pump is adjusted such that an undershoot condition and an overshoot condition of the pulse width modulated signal is minimized.

27. The regulator of claim 26, wherein an input of the comparator circuit comprises an output of the charge pump.

28. The regulator of claim 26, wherein an input of the latch circuit comprises the pulse width modulated signal.

29. The regulator of claim 28, wherein the latch circuit transmits a first latch signal to the charge pump when the pulse width modulated signal is in a high state, wherein the first latch signal prevents the overshoot condition.

30. The regulator of claim 29, wherein the first latch signal prevents the output of the charge pump from increasing further.

31. The regulator of claim 28, wherein the latch circuit transmits a second latch signal to the charge pump when the pulse width modulated voltage is in a low state, wherein the second latch signal prevents the undershoot condition.

32. The regulator of claim 31, wherein the second latch signal prevents the output of the charge pump from decreasing further.

33. The regulator of claim 26, wherein the latch circuit comprises:

a first SR latch;

a second SR latch, wherein an input of the second SR latch comprises the pulse width modulated signal;

a first gate, wherein an input of the first gate comprises an output from the second SR latch and an input signal, wherein an output of the first gate comprises a first latch signal to the charge pump, wherein the first latch signal prevents the overshoot condition; and

a second gate, wherein an input of the second gate comprises an output from the first SR latch and the input signal, wherein an output of the second gate comprises a second latch signal to the charge pump, wherein the second latch signal prevents the undershoot condition.

34. The regulator of claim 33, wherein the latch circuit further comprises:

a first D flip-flop coupled between the first SR latch and the second gate; and

a second D flip-flop coupled between the second SR latch and the first gate.

35. The regulator of claim 26, wherein the comparator circuit comprises:

a clock circuit; and

an inverter coupled to an output of the clock circuit.

36. The regulator of claim 26, wherein the comparator circuit comprises:

a clock circuit; and

a pulse generator coupled to an input of the clock circuit.