Level shifter utilizing input controlled zero threshold blocking transistors

• US 20050134312A1
• Filed: 06/03/2004
• Published: 06/23/2005
• Est. Priority Date: 12/17/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Seo, Jin-Ho
• Granted Patent: US 7,053,656 B2
• Time in Patent Office: Days
• US Class Current: 326/81
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 19/09485 with active depletion transistors

Abstract

Level shifter circuits include zero threshold transistors that reduce a voltage seen by a switching transistor of the level shifter circuits and may increase blocking of static current in the level shifter circuit. The zero threshold transistors are controlled based on the input to the level shifter circuit. Thin oxide transistors may be used to provide low threshold voltages for the switching transistors. Additional level shifter circuits include serially connected zero threshold transistors that act as switching transistors in a current mirror or latch-type level shifter circuit.

Claims

1. A level shifter for shifting an input signal from a first power domain having a first supply voltage to a second power domain having a second supply voltage, comprising:

a current mirror circuit that provides an output signal in the second power domain, the current mirror comprising;

first and second p-type transistors coupled to the second supply voltage;

first and second zero threshold n-type transistors coupled to respective ones of the first and second p-type transistors;

first and second n-type transistors coupled to respective ones of the first and second p-type transistors through respective ones of the first and second zero threshold transistors, the first and second n-type transistors having

a threshold voltage based on the first supply voltage; and

a switching control circuit utilizing the first supply voltage that controls the first zero threshold transistor responsive to the input signal.

2. The level shifter circuit of claim 1, wherein the switching control circuit comprises a delay circuit configured to delay the input signal to provide a delayed input signal to control the first zero threshold transistor.

3. The level shifter of claim 2, further comprising:

a first inverter utilizing the first supply voltage and configured to receive the input signal and provide an inverted input signal to the first n-type transistor;

a second inverter utilizing the first supply voltage and configured to receive the inverted input signal and provide a buffered input signal to the second n-type transistor; and

a third inverter utilizing the second supply voltage and to provide the output signal.

4. The level shifter of claim 3, wherein the delay circuit comprises at least two series inverters utilizing the first supply voltage.

5. The level shifter of claim 3, wherein the delay circuit comprises:

a fourth inverter utilizing the first supply voltage and configured to receive the input signal and provide a second inverted input signal;

a NOR gate utilizing the first supply voltage and configured to receive the input signal and the second inverted input signal and provide a logical NOR of the input signal and the second inverted input signal to the first zero threshold transistor.

6. The level shifter of claim 3, further comprising a third p-type transistor having a gate coupled to the output of the third inverter and that couples the second supply voltage to the input of the third inverter.

7. The level shifter of claim 3, further comprising a fourth p-type transistor having a gate coupled to the input of the third inverter and couples the second supply voltage to the gates of the first and the second p-type transistors.

8. The level shifter of claim 3, wherein a gate of the second zero threshold transistor is coupled to the output of the second inverter.

9. The level shifter of claim 3, wherein a gate of the second zero threshold transistor is coupled to the first supply voltage.

10. The level shifter of claim 2, wherein the delay circuit has a delay corresponding to a delay between a transition in the input signal and a corresponding transition in the output signal.

11. The level shifter of claim 3, wherein the delay circuit has a delay corresponding to a delay between a transition in an output of the first inverter and a corresponding transition in the output signal.

12. The level shifter of claim 1, wherein a voltage between the source and drain of the first and second n-type transistors is limited to the first supply voltage minus a threshold voltage of the corresponding first and second zero threshold transistors.

13. A level shifter for shifting an input signal from a first power domain having a first supply voltage to a second power domain having a second supply voltage, comprising:

first and second cross-coupled p-type transistors coupled to the second supply voltage;

first and second zero threshold n-type transistors serially coupled to the first p-type transistor and responsive to an inverted input signal; and

third and fourth zero threshold n-type transistors serially coupled to the second p-type transistor and responsive to an buffered input signal.

14. The level shifter of claim 13, wherein a gate oxide of the first and second cross-coupled p-type transistors and the first, second, third and fourth zero threshold transistors is substantially the same.

15. The level shifter of claim 13, further comprising:

a first inverter utilizing the first supply voltage and configured to receive the input signal and provide the inverted input signal to the first and second zero threshold transistors;

a second inverter utilizing the first supply voltage and configured to receive the inverted input signal and provide the buffered input signal to the third and fourth zero threshold transistors; and

a third inverter utilizing the second supply voltage and to provide the output signal.

16. A level shifter for shifting an input signal from a first power domain having a first supply voltage to a second power domain having a second supply voltage, comprising:

first and second p-type transistors coupled to the second supply voltage having connected gate electrodes;

first and second zero threshold n-type transistors serially coupled to the first p-type transistor and responsive to an inverted input signal;

third and fourth zero threshold n-type transistors serially coupled to the second p-type transistor and responsive to an buffered input signal; and

a switching control circuit utilizing the first supply voltage that controls the first zero threshold transistor responsive to the input signal.

17. The level shifter of claim 16, wherein a gate oxide of the first and second p-type transistors and the first, second, third and fourth zero threshold transistors is substantially the same.

18. The level shifter of claim 16, further comprising:

a first inverter utilizing the first supply voltage and configured to receive the input signal and provide the inverted input signal to the first and second zero threshold transistors;

a second inverter utilizing the first supply voltage and configured to receive the inverted input signal and provide the buffered input signal to the third and fourth zero threshold transistors; and

a third inverter utilizing the second supply voltage and to provide the output signal.

19. The level shifter of claim 18, wherein the switching control circuit comprises at least two series inverters utilizing the first supply voltage.

20. The level shifter of claim 18, wherein the switching control circuit comprises:

a fourth inverter utilizing the first supply voltage and configured to receive the input signal and provide a second inverted input signal;

a NOR gate utilizing the first supply voltage and configured to receive the input signal and the second inverted input signal and provide a logical NOR of the input signal and the second inverted input signal to the first zero threshold transistor.

21. The level shifter of claim 18, further comprising a third p-type transistor having a gate coupled to the output of the third inverter and that couples the second supply voltage to the input of the third inverter.

22. The level shifter of claim 18, further comprising a fourth p-type transistor having a gate coupled to the input of the third inverter and couples the second supply voltage to the gates of the first and the second p-type transistors.

23. The level shifter of claim 16, wherein the switching control circuit comprises a delay circuit that has a delay corresponding to a delay between a transition in the input signal and a corresponding transition in the output signal.