Method and circuit for translating a differential signal to complmentary CMOS levels

• US 20050134314A1
• Filed: 12/17/2004
• Published: 06/23/2005
• Est. Priority Date: 12/18/2003
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Jeffrey W. Waldrip, Matthew S. Berzins, Stephen M. Prather
• Inventors: Berzins, Matthew S., Prather, Stephen M., Waldrip, Jeffrey W.
• Granted Patent: US 7,173,453 B2
• Time in Patent Office: Days
• US Class Current: 326/86
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

A circuit according to some embodiments of the invention includes a first differential to single ended translator having a first output, a second differential to single ended translator having a second output, and a latch coupled to the first output and the second output, where the latch is configured to select the slower of the first output and the second output.

Claims

1. A circuit comprising:

a first amplifier having a first output;

a second amplifier having a second output; and

a latch coupled to the first output and the second output, the latch configured to change an output state when a slower one of the first and second outputs arrives at the latch.

2. The circuit of claim 1, further comprising a differential input buffer having outputs, wherein the outputs of the differential input buffer are coupled to the first amplifier and to the second amplifier.

3. The circuit of claim 2, the first amplifier comprising a first differential-to-single-ended amplifier and the second amplifier comprising a second differential-to-single-ended amplifier.

4. The circuit of claim 3, wherein the first and second differential-to-single-ended amplifiers are cross-connected.

5. The circuit of claim 4, wherein the first and second differential-to-single-ended amplifiers are well-matched.

6. The circuit of claim 1, the latch comprising:

a first inverter coupled to the first output; and

a second inverter coupled to the first inverter, wherein the second inverter is larger than the first inverter.

7. The circuit of claim 6, wherein the second inverter is approximately twice as large as the first inverter.

8. A level translator circuit comprising:

a first stage configured to buffer a pair of differential inputs;

a second stage coupled to the first stage and configured to output a rising edge and a falling edge in response to a transition in the pair of differential inputs; and

a third stage coupled to the second stage and having a pair of outputs, the pair of outputs configured to switch states in response to the arrival of a slower one of the rising and falling edges.

9. The level translator circuit of claim 8, the second stage consisting of a first differential-to-single-ended amplifier and a second differential-to-single-ended amplifier.

10. The level translator circuit of claim 9, wherein the first differential-to-single-ended amplifier and the second differential-to-single-ended-amplifier are cross-connected.

11. The level translator circuit of claim 9, the third stage comprising a latch that is configured to be tripped only when both of its inputs have opposite logic values.

12. The level translator circuit of claim 11, the latch comprising:

a first inverter coupled to an output of the first differential-to-single-ended amplifier;

a second inverter coupled to an output of the first inverter;

a third inverter coupled to an output of the second differential-to-single-ended amplifier;

and a fourth inverter coupled to an output of the third inverter.

13. The level translator circuit of claim 12, wherein the first and third inverters are smaller than the second and fourth inverters, respectively.

14. The level translator circuit of claim 13, wherein the first and third inverters are approximately half the size of the second and fourth inverters, respectively.

15. A method comprising:

generating a first intermediate signal and a second intermediate signal in response to a transition of a pair of differential input signals, the first intermediate signal delayed with respect to the second intermediate signal;

applying the first intermediate signal and the second intermediate signal as inputs to a latch;

switching an output of the latch only when the first intermediate signal and the second intermediate signal have opposite logic values.

16. The method of claim 15, wherein generating the first intermediate signal and the second intermediate signal comprises buffering the pair of differential input signals.

17. The method of claim 16, wherein generating the first intermediate signal and the second intermediate signal further comprises applying the buffered pair of differential input signals to a pair of differential-to-single-ended amplifiers.

18. The method of claim 17, wherein generating the first intermediate signal and the second intermediate signal further comprises applying the buffered pair of differential input signal to a pair of differential-to-single-ended amplifiers that are cross-connected.

19. The method of claim 15, wherein applying the first intermediate signal and the second intermediate signal as inputs to a latch comprises:

applying the first intermediate signal as an input to a first inverter that is smaller than a second inverter that is coupled to an output of the first inverter; and

applying the second intermediate signal as an input to a third inverter that is smaller than a fourth inverter that is coupled to an output of the third inverter.

20. The method of claim 19, wherein the first inverter and the third inverter are approximately half as large as the second inverter and the fourth inverter, respectively.