Single event transient filter for comparator

• US 20050134323A1
• Filed: 12/23/2003
• Published: 06/23/2005
• Est. Priority Date: 12/23/2003
• Status: Abandoned Application

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Nash, Timothy J.
• Application Number:
  US10/745,124
• Publication Number:
  US 20050134323A1
• Time in Patent Office: Days
• US Class Current: 327/40
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08

Abstract

A R-C low pass filter is used in series with a Schmitt-trigger to form a mask for single event transients (SETs) in a comparator. Transients are masked to logic devices attached to an output of the comparator. A mask time is determined in part by the time constant of the R-C filter, and in part by hysteresis trip points of the Schmitt-trigger input. An inverter provides a stable logic level edge rate, which may have been affected by the R-C filter. In a further embodiment, a reverse biased diode is positioned to bypass the filter when the comparator output is low.

Claims

1. A circuit comprising:

a comparator having two inputs and a comparator output;

an RC delay circuit coupled to the comparator output;

a feedback resistor coupled between the comparator output and one of the inputs; and

a logic device coupled to an output of the RC delay circuit to provide a logic device output having clean edges, wherein the RC delay circuit has an RC time constant sufficient to prevent single event transients from adversely affecting the logic device output.

2. The circuit of claim 1 wherein the logic device comprises a Schmitt-trigger inverter that provides clean CMOS edge output.

3. The circuit of claim 1 wherein the resistance of the first resistor contributes to the RC time constant of the RC delay circuit.

4. The circuit of claim 3 wherein the comparator has a second resistor coupled between the comparator output and a voltage supply, wherein the resistance of the second resistor contributes to the RC time constant of the RC delay circuit.

5. The circuit of claim 4 wherein the RC delay circuit comprises a third resistor and a capacitor coupled to ground, and between the third resistor and an input of the logic device, wherein the RC time constant is a function of a thevenin resistance of the feedback, second and third resistors.

6. A circuit comprising:

a comparator having two inputs and a comparator output;

an RC delay circuit coupled to the comparator output;

a bypass coupled to the RC delay circuit; and

a logic device coupled to an output of the RC delay circuit to provide a logic device output having clean edges, wherein the RC delay circuit has an RC time constant sufficient to prevent single event transients from adversely affecting the desired logic device output.

7. The circuit of claim 6, wherein the bypass comprises a reverse biased diode.

8. The circuit of claim 7 wherein the reverse biased diode is coupled across a resistor of the RC delay circuit.

9. A device that reduces effects of single event transients on a comparator output, the device comprising:

means for comparing inputs to provide a comparator output;

means for providing the comparator output to a RC delay circuit having an RC time constant sufficient to prevent single event transients from adversely affecting the desired logic device output; and

means for inverting an output of the RC delay circuit to provide an output having sharp CMOS edges.

10. A method of reducing effects of single event transients on a comparator output, the method comprising:

comparing inputs to provide a comparator output;

providing the comparator output to a RC delay circuit having an RC time constant sufficient to prevent single event transients from adversely affecting the desired logic device output; and

inverting an output of the RC delay circuit to provide an output having sharp CMOS edges.

11. The method of claim 10 and further comprising bypassing the RC delay circuit when the comparator output is low.