Semiconductor memory device which compensates for delay time variations of multi-bit data

• US 20050135164A1
• Filed: 12/14/2004
• Published: 06/23/2005
• Est. Priority Date: 12/18/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Chan-kyung
• Granted Patent: US 7,227,808 B2
• Time in Patent Office: Days
• US Class Current: 365/194
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/1093 Input synchronization

Abstract

A memory device compensates for delay time variations among multi-bit data. The device includes a first stage and a second stage of data storage units. The first stage of data storage units store first to nth data bits in response to a latch clock signal. The second stage of data storage units store the first to nth data contents output from the first stage of data storage units in response to a reference clock signal. The latch clock signal is obtained by delaying the reference clock signal. The latch clock signal includes first to nth sub latch signals. The sub latch signals are generated at different times according to propagation delay time periods of the corresponding first to nth data contents.

Claims

1. A memory device, comprising:

a first data storage unit adapted to store first to nth data bits input into the first data storage unit in response to a latch clock signal; and

a second data storage adapted to store the first to nth data bits output from the first data storage unit in response to a reference clock signal,

wherein the latch clock signal is obtained by delaying the reference clock signal.

2. The memory device of claim 1, wherein the latch clock signal includes first to nth sub latch clock signals corresponding to the first to nth data bits, and wherein the first to nth sub latch clock signals are generated at different times according to propagation delay time periods of the first to nth data bits.

3. The memory device of claim 2, further comprising first to nth programmable delays which are adapted to delay the reference clock signal to generate the first to nth sub latch clock signals, respectively, and wherein the first data storage unit includes first to nth storage elements which are adapted to store the first to nth data bits in response to the first to nth sub latch clock signals, respectively.

4. The memory device of claim 3, wherein the first to nth programmable delays are adapted to determine delay times of the reference clock signal according to propagation delay times of the first to nth data applied to the first to nth programmable delays.

5. The memory device of claim 3, wherein the first to nth programmable delays are adapted to generate the first to nth sub latch clock signals according to a state of a fuse.

6. The memory device of claim 3, wherein the first to nth programmable delays are adapted to generate delay the first to nth sub latch clock signals according to MRS (Mode Register Set) data in the memory device.

7. The memory device of claim 1, wherein the number of bits of data input into the semiconductor memory device is selectable according to an operating mode of the semiconductor memory device.

8. A memory device having a plurality of data paths for receiving data, wherein the data paths comprise:

a plurality of data storage units adapted to store data, including

a first stage of data storage units adapted to store the data in response to a latch clock signal, and

at least a second stage of data storage units adapted to store the data output from the first stage of data storage units in response to a reference clock signal; and

delay units adapted to delay the reference clock signal and output the latch clock signal.

9. The memory device as claimed in claim 8, wherein the latch clock signal includes a plurality of sub latch clock signals each corresponding to one of the plurality of data paths, and wherein the sub latch clock signals are generated at different times according to propagation delay times of the data input into the corresponding data paths.

10. The semiconductor memory device as claimed in claim 8, wherein the delay units are programmable.

11. The semiconductor memory device as claimed in claim 10, wherein the plurality of programmable delay units are adapted to determine delay times of the reference clock signal according to propagation delay times of the data input into a corresponding data path.

12. The semiconductor memory device as claimed in claim 10, wherein the latch clock signal includes a plurality of sub latch clock signals, and wherein the programmable delay units are adapted to generate the plurality of sub latch clock signals according to a state of at least one fuse.

13. The semiconductor memory device as claimed in claim 10, wherein the programmable delay units are adapted to generate first to nth sub latch clock signals according to MRS (Mode Register Set) data.

14. The semiconductor memory device as claimed in claim 8, wherein a number of data paths which receive data is selectable according to an operating mode of the semiconductor memory device.

15. A memory device having a plurality of data paths for receiving data, wherein the data paths comprise a plurality of data storage units adapted to store data, including;

a first stage of data storage units adapted to asynchronously store the data; and

at least one second stage of data storage units adapted to synchronously store the data output from the first stage of data storage units.

16. The semiconductor memory device as claimed in claim 15, wherein the first stage of data storage units are adapted to store data in response to a latch clock signal, and wherein the second stage of data storage units are adapted to store the data output from the first data storage units in response to a reference clock signal.

17. The semiconductor memory device as claimed in claim 16, wherein the latch clock signal comprises a plurality of sub latch clock signals each corresponding to one of the plurality of data paths, wherein each sub latch clock signal is obtained by delaying the reference clock signal, and wherein each sub latch clock signal is generated at a different time according to a propagation delay time of the data input in the corresponding data path.

18. The semiconductor memory device as claimed in claim 17, further including a plurality of programmable delay units which are adapted to delay the reference clock signal to generate the sub latch clock signals.

19. The semiconductor memory device as claimed in claim 18, wherein each of the programmable delays corresponds to one of the data paths and is adapted to determine a delay time of the reference clock signal according to the propagation delay time of the data input into the corresponding data path.

20. The semiconductor memory device as claimed in claim 19, wherein the programmable delay units are adapted to generate the sub latch clock signals according to a state of a fuse.

21. The semiconductor memory device as claimed in claim 19, wherein the programmable delay units are adapted to delay the reference clock signal, generating the sub latch clock signals according to MRS (Mode Register Set) data.

22. The semiconductor memory device as claimed in claim 15, wherein a number of data paths which receive data is selectable according to an operating mode of the semiconductor memory device.