Interface command architecture for synchronous flash memory

• US 20050135180A1
• Filed: 12/09/2004
• Published: 06/23/2005
• Est. Priority Date: 06/30/2000
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Application Number:
  US11/008,096
• Publication Number:
  US 20050135180A1
• Time in Patent Office: Days
• US Class Current: 365/230.60
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device comprises an array of non-volatile memory cells, and a command register to store command data used to control flash memory operations. In operation, the command register is loaded by initiating a command register load operation using a predefined combination of a column address strobe (CAS#) signal, a row address strobe (RAS#) signal, and a write enable (WE#) signal.

Claims

1. A synchronous flash memory device comprising:

an array of non-volatile memory cells; and

a command register to store command data used to control flash memory operations, wherein the command register is coupled to receive the command data through memory address connections during a load command register operating mode that is initiated using a predetermined configuration of an SDRAM column address strobe (CAS) signal, an SDRAM row address strobe (RAS) signal, and an SDRAM write enable (WE) signal such that additional, external dedicated control signals are not required to perform flash memory operations.

3. The synchronous flash memory device of claim 1 wherein the load command register operating mode is initiated when the CAS signal is low, the RAS signal is low, and the WE signal is high.

4. The synchronous flash memory device of claim 1 wherein the flash memory operations comprises at least one operation selected from the group comprising:

reading a memory device configuration register;

reading a status register of the memory device;

clearing the status register;

performing an erase setup operation;

performing a write setup operation;

protecting a block of the array of memory cells;

providing a memory device write protection operation;

unprotecting the block of the array of memory cells;

writing data to a mode register of the memory device; and

erasing data from the mode register.

2. (canceled)

5. A synchronous flash memory device comprising:

an array of non-volatile memory cells arranged in addressable blocks;

external address connections to receive externally provided address data;

a status register to store memory device status data;

a mode register to store mode data used to set a mode of the synchronous flash memory device; and

a command register, coupled to an external SDRAM column address strobe (CAS) signal, row address strobe (RAS) signal, and write enable (WE) signal, to store command data used to control flash memory operations, wherein the command register is coupled to receive the command data through the external memory address connections in response to a load command that is a predefined configuration of the CAS, the RAS, and the WE signals such that additional, external dedicated control signals are not required to perform flash memory operations.

7. The synchronous flash memory device of claim 5 wherein the load command is a combination of an asserted CAS signal, an asserted RAS signal, and an asserted WE signal.

8. The synchronous flash memory device of claim 5 wherein the load command is equivalent to a refresh command of a synchronous dynamic random access memory (SDRAM).

9. The synchronous flash memory device of claim 5 wherein the flash memory operations comprises at least one operation selected from the group comprising:

performing a read operation of the status register;

clearing the status register;

performing an erase setup operation;

performing a write setup operation;

controlling a write protection of the array of non-volatile memory cells; and

controlling the mode register.

6. (canceled)

10. A synchronous flash memory device comprising:

an array of non-volatile memory cells; and

a command register, coupled to an external SDRAM column address strobe signal (CAS), row address strobe signal (RAS) and write enable signal (WE), to store data commands used to control flash memory operations, wherein the command register is coupled to receive the command data in response to a load command that is equivalent to a refresh command of a synchronous dynamic random access memory (SDRAM) configuration of the CAS, the RAS, and the WE such that additional, external dedicated control signals are not required to perform flash memory operations.

11. (canceled)

12. A synchronous data system comprising:

a memory controller coupled to external memory address connections; and

a synchronous flash memory device coupled to the memory controller and SDRAM column address strobe (CAS), row address strobe (RAS), and write enable (WE) signals, the device comprising,

an array of non-volatile memory cells, and

a command register to store data commands provided by the memory controller over the memory address connections and used to control flash memory operations in response to a load command that is equivalent to an SDRAM refresh command configuration of the CAS, the RAS, and the WE such that additional, external dedicated control signals are not required to perform flash memory operations.

15. The synchronous data system of claim 12 wherein the synchronous flash memory further comprises:

a status register to store memory device status data; and

a mode register to store mode data used to set a mode of the synchronous flash memory device.

16. The synchronous data system of claim 15 wherein the flash memory operations comprises at least one operation selected from the group comprising:

performing a read operation of the status register;

clearing the status register;

performing an erase setup operation;

performing a write setup operation;

controlling a write protection of the array of non-volatile memory cells; and

controlling the mode register.

13. (canceled)

14. The synchronous data system of claim 13 wherein the load command is a combination of an asserted CAS signal, an asserted RAS signal, and an asserted WE signal.

17. A method of providing commands in a synchronous flash memory, the method comprising:

initiating a command register load operation using a predefined combination of a column address strobe (CAS#) signal, a row address strobe (RAS#) signal, and a write enable (WE#) signal; and

loading command data into the command register using address connections of the synchronous flash memory in response to the command register load operation such that additional external dedicated control signals are not required to perform flash memory operations.

18. The method of claim 17 wherein the command register is loaded when the CAS# signal is asserted, the RAS# signal is asserted, and the WE# signal is deasserted.

19. The method of claim 17 wherein the predefined combination is equivalent to the RAS#, CAS# and WE# combination used to perform a refresh operation of a synchronous dynamic random access memory (SDRAM).

20. The method of claim 17 further comprising performing a memory operation in response to the command data, the memory operation selected from the group comprising:

performing a read operation of a memory status register;

clearing the status register;

performing an erase setup operation;

performing a write setup operation;

controlling a write protection of an array of non-volatile memory cells; and

controlling a mode register.

21. A method of operating a synchronous flash memory, the method comprising:

initiating a command register load operation using a predefined combination of an asserted column address strobe (CAS#) signal, an asserted row address strobe (RAS#) signal, and a deasserted write enable (WE#) signal; and

loading command data into the command register using address connections of the synchronous flash memory in response to the command register load operation so that additional, external dedicated control signals are not required to perform flash memory operations; and

performing a memory operation in response to the command data.

22. The method of claim 21 wherein the memory operation selected from the group comprising:

reading a memory device configuration register;

reading a status register of the memory device;

clearing the status register;

performing an erase setup operation;

performing a write setup operation;

protecting a block of the array of memory cells;

providing a memory device write protection operation;

unprotecting the block of the array of memory cells;

writing data to a mode register of the memory device; and

erasing data from the mode register.