Chip-to-chip communication system using an ac-coupled bus and devices employed in same

• US 20050135182A1
• Filed: 12/23/2004
• Published: 06/23/2005
• Est. Priority Date: 09/17/1999
• Status: Active Grant

• Current Assignee: Alfredo Moncayo, Bruno W Garlepp, Donald V. Perino, Haw-Jyh Liaw, Kevin Donnelly, Richard M. Barth
• Original Assignee: Alfredo Moncayo, Bruno W Garlepp, Donald V. Perino, Haw-Jyh Liaw, Kevin Donnelly, Richard M. Barth
• Inventors: Barth, Richard M., Garlepp, Bruno W., Liaw, Haw-Jyh, Moncayo, Alfredo, Donnelly, Kevin, Perino, Donald V.
• Granted Patent: US 7,130,944 B2
• Time in Patent Office: Days
• US Class Current: 365/230.60
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A chip-to-chip communication system and interface technique. A master and at least two devices are interconnected with a signal line of a high speed bus. A capacitive coupling element, for example a diode, is employed to capacitively couple the interface of the device to the signal line. By employing the capacitive coupling element, along with a suitable signaling technique which supports capacitive information transfer, high speed rates of information transfer between the master and device over the signal line are achieved.

Claims

1. A chip-to-chip system comprising:

an external bus having a plurality of signal lines;

a plurality of devices, including a first device and a second device, coupled to the external bus, wherein the first device includes an input receiver which is coupled to a first signal line of the external bus and the second device includes an input receiver which is coupled to the first signal line of the external bus;

a first capacitive coupling element, disposed between the input receiver of the first device and the first signal line, the first capacitive coupling element electrically couples the input receiver of the first device to the first signal line to receive data on the external bus; and

a second capacitive coupling element, disposed between the input receiver of the second device and the first signal line, the second capacitive coupling element electrically couples the input receiver of the second device to the first signal line to receive data on the external bus.

2. The chip-to-chip system of claim 1 wherein the first device is a memory device, the second device is a memory controller.

3. The chip-to-chip system of claim 1 wherein the first and second capacitive coupling elements are selected from a group consisting of an integrated capacitor, a discrete capacitor, a microwave coupler, and at least one diode device.

4. The chip-to-chip system of claim 1 wherein the first capacitive coupling element is an integrated circuit device and the capacitor is integrated on the first device.

5. The chip-to-chip system of claim 1 wherein the first capacitive coupling element is a diode element.

6. The chip-to-chip system of claim 5 wherein the diode element operates in a reverse bias state when the first device receives data on the first signal line to thereby capacitively couple the first device to the first signal line.

7. The chip-to-chip system of claim 5, wherein the first device further includes an output driver which is coupled to the first signal line via the diode element.

8. The chip-to-chip system of claim 7 wherein the diode element operates in a forward biased state when the first device provides data on the first signal line to thereby directly couple the first device to the first signal line.

9. The chip-to-chip system of claim 8 wherein the first device is an integrated circuit and the diode element is integrated on the device.

10. The chip-to-chip system of claim 7 wherein the output driver is a pull-up type driver and the diode element is a forward biased diode device when the first device provides data on the external signal line.

11. The chip-to-chip system of claim 7 wherein the output driver is a pull-down type driver and the diode element is a reverse biased diode device when the first device receives data on the external signal line.

12. The chip-to-chip system of claim 7 wherein the output driver is a push-pull type driver having an output and wherein the diode element includes a first diode device having an anode coupled to the external signal line and a cathode coupled to the output of the output driver and a second diode device having an anode coupled to the output of the output driver and a cathode coupled to the external signal line.

13. An integrated circuit device comprising:

an input receiver having an input; and

a diode element disposed between the input of the input receiver and an external signal line to capacitively couple data on the external signal line to the input of the input receiver.

14. The integrated circuit device of claim 13 wherein the diode element operates in a reverse bias state when the integrated circuit device receives data on the external signal line.

15. The integrated circuit device of claim 13 further including an output driver having an output wherein the diode device is disposed between the output of the output driver and the external signal line.

16. The integrated circuit device of claim 15 wherein the output driver is a pull-up type driver and the diode element is a forward biased diode device when the integrated circuit device provides data on the external signal line.

17. The integrated circuit device of claim 15 wherein the output driver is a pull-down type driver and the diode element is a reverse biased diode device when the integrated circuit device receives data on the external signal line.

18. The integrated circuit device of claim 15 wherein the output driver is a push-pull type driver having an output and wherein the diode element includes a first diode device having an anode coupled to the external signal line and a cathode coupled to the output of the output driver and a second diode device having an anode coupled to the output of the output driver and a cathode coupled to the external signal line.

19. The integrated circuit device of claim 13 wherein the diode element operates in a reverse bias state when the integrated circuit device receives data on the signal line and in a forward bias state when the device provides data on the signal line.

20. The integrated circuit device of claim 13 wherein the diode is on the integrated circuit.